Switch to B-enabled rocket configs globally

generators/chipyard/src/main/scala/config/AraConfigs.scala

@@ -6,14 +6,14 @@ import saturn.common.{VectorParams}
 // Rocket-integrated configs
 class V4096Ara2LaneRocketConfig extends Config(
   new ara.WithAraRocketVectorUnit(4096, 2) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 
 class V8192Ara4LaneRocketConfig extends Config(
   new ara.WithAraRocketVectorUnit(8192, 4) ++
   new chipyard.config.WithSystemBusWidth(128) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -17,7 +17,7 @@ class ChipLikeRocketConfig extends Config(
   // Set up tiles
   //==================================
   new freechips.rocketchip.rocket.WithAsynchronousCDCs(depth=8, sync=3) ++ // Add async crossings between RocketTile and uncore
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++                      // 1 RocketTile
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++                      // 1 RocketTile
 
   //==================================
   // Set up I/O

generators/chipyard/src/main/scala/config/ChipletConfigs.scala

@@ -35,7 +35,7 @@ class SymmetricChipletRocketConfig extends Config(
     replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
   ) ++
   new testchipip.soc.WithOffchipBus ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
@@ -71,7 +71,7 @@ class RocketCoreChipletConfig extends Config(
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // LLC-only chiplet

generators/chipyard/src/main/scala/config/ClockingConfigs.scala

@@ -14,7 +14,7 @@ import testchipip.soc.{OBUS}
 // Note: This is what designs inheriting from AbstractConfig do by default
 class DefaultClockingRocketConfig extends Config(
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This is a more physically realistic approach, normally we can't punch out a separate
@@ -23,12 +23,12 @@ class DefaultClockingRocketConfig extends Config(
 // clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info
 class ChipLikeClockingRocketConfig extends Config(
   new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single
 // clock input pin.
 class SingleClockBroadcastRocketConfig extends Config(
   new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -8,27 +8,27 @@ import org.chipsalliance.cde.config.{Config}
 
 class LargeBoomAndRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(1) ++                    // single-core boom
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++         // single rocket-core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class DualLargeBoomAndDualRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
-  new freechips.rocketchip.rocket.WithNBigCores(2) ++  // add 2 rocket cores
+  new freechips.rocketchip.rocket.WithNHugeCores(2) ++  // add 2 rocket cores
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DualBoomAndSingleRocket
 class DualLargeBoomAndSingleRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++  // add 1 rocket core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++  // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DualBoomAndSingleRocket
 
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
   new freechips.rocketchip.rocket.WithNSmallCores(1) ++    // Add a small "control" core
   new boom.v3.common.WithNLargeBooms(1) ++                 // Add 1 boom core
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++      // add 1 rocket core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++      // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala

@@ -10,51 +10,51 @@ import org.chipsalliance.cde.config.{Config}
 class FFTRocketConfig extends Config(
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++              // TODO: hack around dontTouch not working in SFC
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: FFTRocketConfig
 
 // DOC include start: GCDTLRocketConfig
 class GCDTLRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDTLRocketConfig
 
 // DOC include start: GCDAXI4BlackBoxRocketConfig
 class GCDAXI4BlackBoxRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++            // Use GCD blackboxed verilog, connect by AXI4->Tilelink
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDAXI4BlackBoxRocketConfig
 
 // DOC include start: InitZeroRocketConfig
 class InitZeroRocketConfig extends Config(
   new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++   // add InitZero
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: InitZeroRocketConfig
 
 class StreamingPassthroughRocketConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: StreamingFIRRocketConfig
 class StreamingFIRRocketConfig extends Config (
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: StreamingFIRRocketConfig
 
 class SmallNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("small") ++               // add a small NVDLA
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class LargeNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("large", true) ++         // add a large NVDLA with synth. rams
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class ManyMMIOAcceleratorRocketConfig extends Config(
@@ -63,5 +63,5 @@ class ManyMMIOAcceleratorRocketConfig extends Config(
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala

@@ -8,38 +8,38 @@ import org.chipsalliance.cde.config.{Config}
 
 class SimAXIRocketConfig extends Config(
   new chipyard.harness.WithSimAXIMem ++                     // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class GB1MemoryRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadOnlyRocketConfig extends Config(
   new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: mbusscratchpadrocket
 
 class SbusScratchpadRocketConfig extends Config(
   new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SbusBypassRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++ // Add bypass path to access DRAM incoherently through an address alias
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class QuadChannelRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++      // 4 AXI4 channels
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BroadcastCoherenceRocketConfig extends Config(
   new chipyard.config.WithBroadcastManager ++                 // Use broadcast-based coherence hub
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/NoCConfigs.scala

@@ -101,7 +101,7 @@ class MultiNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
       routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
   new chipyard.config.AbstractConfig
@@ -180,7 +180,7 @@ class SharedNoCConfig extends Config(
         "system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
         "pbus" -> 4))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
   new chipyard.config.AbstractConfig
@@ -216,7 +216,7 @@ class SbusRingNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }),
       routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.AbstractConfig
 )
@@ -260,7 +260,7 @@ class SbusMeshNoCConfig extends Config(
     ),
     beDivision = 4
   ), inlineNoC = true) ++
-  new freechips.rocketchip.rocket.WithNBigCores(12) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(12) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig
@@ -286,6 +286,6 @@ class QuadRocketSbusRingNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
       routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(4) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(4) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -10,44 +10,44 @@ import freechips.rocketchip.subsystem.{MBUS}
 class LargeSPIFlashROMRocketConfig extends Config(
   new chipyard.harness.WithSimSPIFlashModel(true) ++        // add the SPI flash model in the harness (read-only)
   new chipyard.config.WithSPIFlash ++                       // add the SPI flash controller
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SmallSPIFlashRocketConfig extends Config(
   new chipyard.harness.WithSimSPIFlashModel(false) ++       // add the SPI flash model in the harness (writeable)
   new chipyard.config.WithSPIFlash(0x100000) ++             // add the SPI flash controller (1 MiB)
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SimBlockDeviceRocketConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++                // drive block-device IOs with SimBlockDevice
   new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to peripherybus
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
   new chipyard.harness.WithBlockDeviceModel ++              // drive block-device IOs with a BlockDeviceModel
   new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to periphery bus
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: GPIORocketConfig
 class GPIORocketConfig extends Config(
   new chipyard.config.WithGPIO ++                           // add GPIOs to the peripherybus
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GPIORocketConfig
 
 class LoopbackNICRocketConfig extends Config(
   new chipyard.harness.WithLoopbackNIC ++                      // drive NIC IOs with loopback
   new icenet.WithIceNIC ++                                     // add an IceNIC
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class MMIORocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class LBWIFRocketConfig extends Config(
@@ -56,14 +56,14 @@ class LBWIFRocketConfig extends Config(
   new testchipip.soc.WithOffchipBus ++
   new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove AXI4 backing memory
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DmiRocket
 
@@ -75,7 +75,7 @@ class dmiCospikeCheckpointingRocketConfig extends Config(
   new chipyard.config.WithNPMPs(0) ++                   // remove PMPs (reduce non-core arch state)
   new freechips.rocketchip.rocket.WithDebugROB ++       // cospike needs wdata given by the unsynth. debug rom
   new freechips.rocketchip.rocket.WithCease(false) ++   // remove xrocket ISA extension
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 
@@ -91,7 +91,7 @@ class ManyPeripheralsRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
   new freechips.rocketchip.subsystem.WithNoMemPort ++        // remove AXI4 backing memory
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class UARTTSIRocketConfig extends Config(
@@ -100,5 +100,5 @@ class UARTTSIRocketConfig extends Config(
   new chipyard.config.WithMemoryBusFrequency(10) ++
   new chipyard.config.WithFrontBusFrequency(10) ++
   new chipyard.config.WithPeripheryBusFrequency(10) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)