Switch to non-cosim vector config in CI

ucb-bar · Aug 6, 2024 · b36cf88 · b36cf88
1 parent e5cf923
commit b36cf88
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Showing 2 changed files with 7 additions and 5 deletions.
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
@@ -71,8 +71,8 @@ mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
 mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
 mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
 mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig"
-mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketCosimConfig"
-mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleCosimConfig"
+mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig"
+mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig"
 
 mapping["constellation"]=" SUB_PROJECT=constellation"
 mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig"

diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
@@ -136,9 +136,11 @@ case $1 in
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/rerocc/tests/rerocc.riscv LOADMEM=1
         ;;
     chipyard-rocketvector|chipyard-shuttlevector)
-	run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
-	run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1
-	;;
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
+        ;;
     tracegen)
         run_tracegen
         ;;