vcs: fix assertions at time 0 (#548) (#551)

It seems that clock=1 at time zero qualifies as a posedge for vcs.
This caused assertions to fire as registers have not yet been reset.

(cherry picked from commit 541ae8c)

Co-authored-by: Wesley W. Terpstra <wesley@sifive.com>

src/main/scala/chiseltest/simulator/ipc/VpiVerilogHarnessGenerator.scala

@@ -24,7 +24,7 @@ private[chiseltest] object VpiVerilogHarnessGenerator {
 
     val codeBuffer = new StringBuilder
     codeBuffer.append(s"module $testbenchName;\n")
-    codeBuffer.append(s"  reg $clockName = 1;\n")
+    codeBuffer.append(s"  reg $clockName = 0;\n")
     toplevel.inputs.foreach { case PinInfo(name, width, _) =>
       codeBuffer.append(s"  reg[${width - 1}:0] $name = 0;\n")
     }