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test for account write access
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@kris-dong
kris-dong committed Mar 21, 2024
1 parent 8c8b38b commit 6e8ced7
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Showing 3 changed files with 106 additions and 12 deletions.
29 changes: 29 additions & 0 deletions src/main/scala/gemmini/Configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -239,6 +239,10 @@ object GemminiConfigs {

val leanPrintfConfig = defaultConfig.copy(dataflow=Dataflow.WS, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true, use_firesim_simulation_counters=true)

val NVDLAConfig = defaultConfig.copy(meshRows = 1, meshColumns = 4, tileRows = 4, tileColumns = 1)

val ReducedNVDLAConfig = defaultConfig.copy(meshRows = 1, meshColumns = 1, tileRows = 4, tileColumns = 4)

}

/**
Expand Down Expand Up @@ -285,6 +289,7 @@ class LeanGemminiPrintfConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
)
})


class DummyDefaultGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.dummyConfig
) extends Config((site, here, up) => {
Expand Down Expand Up @@ -368,3 +373,27 @@ class DualGemminiConfig extends Config((site, here, up) => {
up(BuildRoCC) ++ Seq(int_fn, fp_fn)
}
})

class NVDLAGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.NVDLAConfig
) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq(
(p: Parameters) => {
implicit val q = p
val gemmini = LazyModule(new Gemmini(gemminiConfig))
gemmini
}
)
})

class ReducedNVDLAGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.ReducedNVDLAConfig
) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq(
(p: Parameters) => {
implicit val q = p
val gemmini = LazyModule(new Gemmini(gemminiConfig))
gemmini
}
)
})
65 changes: 60 additions & 5 deletions src/main/scala/gemmini/Mesh.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,24 @@ import chisel3.experimental._
* @param meshRows
* @param meshColumns
*/
//scala code vs chisel code
//generator(genver) vs HW(verilog)
//sequence vs vector
//if vs when
//3D a[[[],[]]]
//val in_a = Input(Vec(meshRows, Vec(tileRows^2, inputType))) //meshRows vector

//val in_a = Input(Vec(meshRows^2, Vec(tileRows, inputType))) //meshRows vector
// val in_a = Input(Vec(meshColumns, Vec(meshRows, Vec(tileRows, inputType)))) //meshRows vector

class Mesh[T <: Data : Arithmetic](inputType: T, outputType: T, accType: T,
df: Dataflow.Value, tree_reduction: Boolean, tile_latency: Int,
max_simultaneous_matmuls: Int, output_delay: Int,
val tileRows: Int, val tileColumns: Int,
val meshRows: Int, val meshColumns: Int) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(meshRows, Vec(tileRows, inputType)))
// val in_a = Input(Vec(meshColumns, Vec(meshRows, Vec(tileRows, inputType)))) //meshRows vector
val in_a = Input(Vec(meshRows, Vec(tileRows, inputType)))//meshRows vector
val in_b = Input(Vec(meshColumns, Vec(tileColumns, inputType)))
val in_d = Input(Vec(meshColumns, Vec(tileColumns, inputType)))
val in_control = Input(Vec(meshColumns, Vec(tileColumns, new PEControl(accType))))
Expand All @@ -36,7 +47,9 @@ class Mesh[T <: Data : Arithmetic](inputType: T, outputType: T, accType: T,
})

// mesh(r)(c) => Tile at row r, column c
// val mesh: Seq[Seq[Tile[T]]] = Seq.fill(meshRows, meshColumns)(Module(new Tile(Vec(,inputType), outputType, accType, df, tree_reduction, max_simultaneous_matmuls, tileRows, tileColumns)))
val mesh: Seq[Seq[Tile[T]]] = Seq.fill(meshRows, meshColumns)(Module(new Tile(inputType, outputType, accType, df, tree_reduction, max_simultaneous_matmuls, tileRows, tileColumns)))
//pass in vec of vec
val meshT = mesh.transpose

def pipe[T <: Data](valid: Bool, t: T, latency: Int): T = {
Expand All @@ -47,14 +60,56 @@ class Mesh[T <: Data : Arithmetic](inputType: T, outputType: T, accType: T,

// Chain tile_a_out -> tile_a_in (pipeline a across each row)
// TODO clock-gate A signals with in_garbage
// for (r <- 0 until meshRows) {
// mesh(r).foldLeft(io.in_a(r)) {
// for (n <- 0 until in_a(0).length-1){
// case (in_a, tile) =>
// tile.io.in_a(n) := ShiftRegister(in_a, tile_latency+1)
// }
// // tile.io.in_a := ShiftRegister(Vec(in_a, inputType), tile_latency+1)
// tile.io.out_a
// }
// }
for (r <- 0 until meshRows) {
mesh(r).foldLeft(io.in_a(r)) {
case (in_a, tile) =>
tile.io.in_a := ShiftRegister(in_a, tile_latency+1)
tile.io.out_a
mesh(r).foldLeft(io.in_a(r)) { case (in_a, tile) =>
// val in_a_length = tileColumns
for (n <- 0 until tileColumns) {
//1st one shift register
tile.io.in_a(n) := ShiftRegister(in_a, tile_latency + 1)
}
tile.io.out_a
//sign the previous tile.io.out_a to be in_a
}
}
for (r <- 0 until meshRows) {
mesh(r).foldLeft(io.in_a(r)) { case (in_a, tile) =>
// val in_a_length = tileColumns
//1st one shift register
tile.io.in_a(0) := ShiftRegister(in_a, tile_latency + 1)
for (n <- 0 until tileColumns) {
in_a
}
tile.io.out_a
//sign the previous tile.io.out_a to be in_a
}
}
// for (r <- 0 until meshRows) {
// mesh(r).foldLeft(io.in_a(r)) {
// case (in_a, tile) =>
// tile.io.in_a := ShiftRegister(in_a, tile_latency+1)
// tile.io.out_a
// }
// }

// val pipelined_a = ?
// for (r <- 0 until meshRows) {

// for (c <- 0 until meshColumns) {
// for (r <- 0 until meshRows) {
// tile.io.in_a(r)(c) := wireInit(Mux(true.B))

// }
// }
// Chain tile_out_b -> tile_b_in (pipeline b across each column)
for (c <- 0 until meshColumns) {
meshT(c).foldLeft((io.in_b(c), io.in_valid(c))) {
Expand Down
24 changes: 17 additions & 7 deletions src/main/scala/gemmini/Tile.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,8 @@ import Util._
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_a = Input(Vec(columns, Vec(rows, inputType)))//2D
// val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))

Expand All @@ -42,17 +43,26 @@ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Valu
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose


// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
//val result = Mux(isGEMV, whenTrue, whenFalse)
// tile(0)(0).io.in_a := WireInit(Mux(true.B, io.in_a(c)(r), tile(r)(c-1).io.out_a)) // Corrected: Changed wireInit to WireInit and fixed in_a access
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
tile(0)(r).io.in_a := io.in_a(0)(r)

for (c <- 0 until columns-1) {
tile(c+1)(r).io.in_a := WireInit(Mux(false.B, io.in_a(c)(r), tile(c)(r).io.out_a))
// tile(r)(c).pe.io.in_a := wireInit(Mux(true.B, in_a(r)(c), tile(r)(c-1).pe.io.out_a))
}
}

// Broadcast 'b' vertically across the Tile
// for (c <- 0 until meshColumns) {
// for (r <- 0 until meshRows) {
// tile.io.in_a(r)(c) := wireInit(Mux(true.B))

// Broadcast 'b' vertically across the Tile n^2 PE, n^2 inputs
// Broadcast 'b' vertically across the Tile n^2 PE, n inputs
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
Expand Down

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