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fpga/app: Fix MAC PTP clock connections in app testbenches
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@alexforencich
alexforencich committed Feb 13, 2024
1 parent 435871c commit b4d6e55
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Showing 3 changed files with 6 additions and 6 deletions.
4 changes: 2 additions & 2 deletions fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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Original file line number Diff line number Diff line change
Expand Up @@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
ifg=12, speed=eth_speed
)

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4 changes: 2 additions & 2 deletions fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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Original file line number Diff line number Diff line change
Expand Up @@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
ifg=12, speed=eth_speed
)

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4 changes: 2 additions & 2 deletions fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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Original file line number Diff line number Diff line change
Expand Up @@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32):
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
ifg=12, speed=eth_speed
)

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