Merge pull request #77 from unihd-cag/iss76

Iss76
unihd-cag · May 11, 2016 · 11b7d53 · 11b7d53
2 parents d808872 + e34c130
commit 11b7d53
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Showing 4 changed files with 18 additions and 17 deletions.
diff --git a/scala-interface/pom.xml b/scala-interface/pom.xml
@@ -1,9 +1,8 @@
-<project xmlns="http://maven.apache.org/POM/4.0.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-	xsi:schemaLocation="http://maven.apache.org/POM/4.0.0 http://maven.apache.org/xsd/maven-4.0.0.xsd">
+<project xmlns="http://maven.apache.org/POM/4.0.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://maven.apache.org/POM/4.0.0 http://maven.apache.org/xsd/maven-4.0.0.xsd">
 	<modelVersion>4.0.0</modelVersion>
 	<groupId>uni.hd.cag.rfg</groupId>
 	<artifactId>rfg-core</artifactId>
-	<version>1.5.0-SNAPSHOT</version>
+	<version>1.5.1-SNAPSHOT</version>
 
 	<!-- use OSI Scala Parent pom to have scala enabled -->
 	<!-- ################# -->
@@ -17,9 +16,9 @@
 	<!-- SCM -->
 	<!-- #### -->
 	<scm>
-		<connection>scm:git:git://gitlab@lebleu/cag-osys/rfg.git</connection>
-		<developerConnection>scm:git:gitlab@lebleu:cag-osys/rfg.git</developerConnection>
-		<url>http://http://lebleu/gitlab/cag-osys/rfg</url>
+		<connection>scm:git:git@github.com:unihd-cag/odfi-rfg.git</connection>
+		<developerConnection>scm:git:git@github.com:unihd-cag/odfi-rfg.git</developerConnection>
+		<url>https://github.com/unihd-cag/odfi-rfg</url>
 		<tag>HEAD</tag>
 	</scm>
 
@@ -48,7 +47,7 @@
 			<plugin>
 				<groupId>org.apache.maven.plugins</groupId>
 				<artifactId>maven-ooxoo-plugin</artifactId>
-				<version>3.1.1-SNAPSHOT</version>
+				<version>3.1.1</version>
 				<dependencies>
 					<dependency>
 						<groupId>com.idyria.osi.wsb</groupId>
@@ -220,15 +219,10 @@
 			<artifactId>aib-core</artifactId>
 			<version>3.1.0</version>
 		</dependency>
-		<dependency>
-			<groupId>com.idyria.osi.tea</groupId>
-			<artifactId>tea</artifactId>
-			<version>3.1.0</version>
-		</dependency>
 		<dependency>
 			<groupId>com.idyria.osi.ooxoo</groupId>
 			<artifactId>ooxoo-core</artifactId>
-			<version>3.1.1-SNAPSHOT</version>
+			<version>3.1.1</version>
 		</dependency>
 		<dependency>
 			<groupId>com.idyria.osi.wsb</groupId>

diff --git a/tcl/generator-verilog/Instances.tm b/tcl/generator-verilog/Instances.tm
@@ -244,7 +244,7 @@ odfi::closures::oproc writeRamModule {ramBlock} {
 # write RF instance
 odfi::closures::oproc writeRFModule {registerfile} {
     odfi::common::println "" $resolve
-	odfi::common::println "[$registerfile name] [$registerfile name]_I (" $resolve
+	odfi::common::println "[lindex [split [file tail [$registerfile getAttributeValue rfg.osys::rfg::file]] "."] 0] [$registerfile name]_I (" $resolve
 	odfi::common::println "	.res_n(res_n)," $resolve
 	odfi::common::println "	.clk(clk)," $resolve
 	odfi::common::println "	.address([$registerfile name]_address)," $resolve

diff --git a/tcl/generator-verilog/VerilogGenerator.tm b/tcl/generator-verilog/VerilogGenerator.tm
@@ -41,11 +41,17 @@ namespace eval osys::rfg::generator::verilog {
             file mkdir $destinationPath
             set ::options $generator
             set registerfiles $registerFile
+            set file_list [$registerFile getAttributeValue rfg.osys::rfg::file]
            	## Read and parse Verilog Template
 
             $registerFile walkDepthFirst {
                 if {[$it isa osys::rfg::RegisterFile]} {
-                    lappend registerfiles $it
+                    if {[lsearch $file_list [$it getAttributeValue rfg.osys::rfg::file]] == -1} {
+                        lappend file_list [$it getAttributeValue rfg.osys::rfg::file]
+                        lappend registerfiles $it
+                        ::puts "This is the file name:"
+                        ::puts [$it getAttributeValue rfg.osys::rfg::file]
+                    }
                 }
                 return true
             }
@@ -54,7 +60,8 @@ namespace eval osys::rfg::generator::verilog {
                 ::puts "VerilogGenerator processing: $::rf > ${destinationPath}[$::rf name].v"
                 namespace eval :: {
                     catch {source ${::osys::rfg::generator::verilog::location}/registerfile_template.tcl} result
-                    $result generate ${dP}[$rf name].v
+                    set name [lindex [split [file tail [$rf getAttributeValue rfg.osys::rfg::file]] "."] 0]
+                    $result generate ${dP}${name}.v
                 }
             }
 

diff --git a/tcl/generator-verilog/registerfile_template.tcl b/tcl/generator-verilog/registerfile_template.tcl
@@ -1216,7 +1216,7 @@ odfi::closures::oproc writeTriggerBlock {object} {
     }
 }
 
-osys::verilogInterface::module [$rf name] {
+osys::verilogInterface::module [lindex [split [file tail [$rf getAttributeValue rfg.osys::rfg::file]] "."] 0] {
     writeAddrComment $rf
     ## Write RegisterFile Signal Interface
     writeVModuleInterface $rf