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SystemVerilog: find instance, more readable
SystemVerilog: give K_INSTANCE to createTag directly SystemVerilog: new test case Add a space in ");" at the end of one of module instantiationsadd
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@@ -0,0 +1,2 @@ | ||
--extras=+q | ||
--sort=no |
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foo input.v /^module foo # (parameter$/;" m | ||
PAR_A input.v /^ PAR_A = 1,$/;" c module:foo | ||
foo.PAR_A input.v /^ PAR_A = 1,$/;" c module:foo | ||
PAR_B input.v /^ PAR_B = 2$/;" c module:foo | ||
foo.PAR_B input.v /^ PAR_B = 2$/;" c module:foo | ||
a input.v /^ input a, b;$/;" p module:foo | ||
foo.a input.v /^ input a, b;$/;" p module:foo | ||
b input.v /^ input a, b;$/;" p module:foo | ||
foo.b input.v /^ input a, b;$/;" p module:foo | ||
top input.v /^module top (\/*AUTOARG*\/$/;" m | ||
a input.v /^ input a; \/\/ To uut3 of foo.v$/;" p module:top | ||
top.a input.v /^ input a; \/\/ To uut3 of foo.v$/;" p module:top | ||
b input.v /^ input b; \/\/ To uut3 of foo.v$/;" p module:top | ||
top.b input.v /^ input b; \/\/ To uut3 of foo.v$/;" p module:top | ||
unused_pin input.v /^ wire unused_pin;$/;" n module:top | ||
top.unused_pin input.v /^ wire unused_pin;$/;" n module:top | ||
uut1 input.v /^ foo uut1 ($/;" i module:top | ||
top.uut1 input.v /^ foo uut1 ($/;" i module:top | ||
uut2 input.v /^ uut2 ($/;" i module:top | ||
top.uut2 input.v /^ uut2 ($/;" i module:top | ||
uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top | ||
top.uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top | ||
uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top | ||
top.uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top | ||
uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top | ||
top.uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top | ||
uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top | ||
top.uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top | ||
uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top | ||
top.uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top | ||
uut8 input.v /^ foo uut8 () ;$/;" i module:top | ||
top.uut8 input.v /^ foo uut8 () ;$/;" i module:top | ||
func_foo input.v /^ function void func_foo(int a);$/;" f module:top | ||
top.func_foo input.v /^ function void func_foo(int a);$/;" f module:top | ||
a input.v /^ function void func_foo(int a);$/;" p function:top.func_foo | ||
top.func_foo.a input.v /^ function void func_foo(int a);$/;" p function:top.func_foo |
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// Include module declaration in a comment | ||
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module foo # (parameter | ||
PAR_A = 1, | ||
PAR_B = 2 | ||
) | ||
(/*AUTOARG*/ | ||
// Inputs | ||
a, b | ||
); | ||
input a, b; | ||
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endmodule: foo | ||
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module top (/*AUTOARG*/ | ||
// Inputs | ||
a, b | ||
); | ||
//begin: AUTOOUTPUTS | ||
/*AUTOOUTPUT*/ | ||
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//begin: AUTOINPUTS | ||
/*AUTOINPUT*/ | ||
// Beginning of automatic inputs (from unused autoinst inputs) | ||
input a; // To uut3 of foo.v | ||
input b; // To uut3 of foo.v | ||
// End of automatics | ||
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//begin: AUTOWIREs | ||
/*AUTOWIRE*/ | ||
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//begin: AUTOREGINPUTs | ||
/*AUTOREGINPUT*/ | ||
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//begin: AUTOREGs | ||
/*AUTOREGINPUT*/ | ||
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//begin: AUTOUNUSEDs | ||
wire unused_pin; | ||
assign unused_pin = |{ | ||
/*AUTOUNUSED*/ | ||
1'b0} ; | ||
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//begin: AUTOTIEOFFs | ||
/*AUTOTIEOFF*/ | ||
foo uut1 ( | ||
// Inputs | ||
a, | ||
b), | ||
uut2 ( | ||
.a (a), | ||
.b (b)); | ||
foo uut3 (/*AUTOINST*/ | ||
// Inputs | ||
.a (a), | ||
.b (b)) ; | ||
foo #(3, 4) | ||
uut4 (/*AUTOINST*/ | ||
// Inputs | ||
.a (a), | ||
.b (b)); | ||
foo #(.PAR_A (5), | ||
.PAR_B (6)) | ||
uut5 (/*AUTOINST*/ | ||
// Inputs | ||
.a (a), | ||
.b (b)); | ||
foo uut6 [10:0](); | ||
foo uut7 [1:0][10:0](); | ||
foo uut8 () ; | ||
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/*! Function Description | ||
* | ||
* \param <name> <description> | ||
* | ||
* \return <return value description> | ||
*/ | ||
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function void func_foo(int a); | ||
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endfunction : func_foo | ||
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endmodule: top |
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