Merge pull request #2680 from hirooih/sv-token-handling

SystemVerilog: handle an identifier include '$'
universal-ctags · Oct 29, 2020 · 6222334 · 6222334
2 parents ed02c0b + 4219047
commit 6222334
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Showing 5 changed files with 135 additions and 102 deletions.
diff --git a/Units/parser-verilog.r/systemverilog-github646.d/expected.tags b/Units/parser-verilog.r/systemverilog-github646.d/expected.tags
@@ -1 +1 @@
-0	input.sv	/^function 0:/;"	f
+function	input.sv	/^function 0:/;"	f
diff --git a/Units/parser-verilog.r/systemverilog-net-var.d/expected.tags b/Units/parser-verilog.r/systemverilog-net-var.d/expected.tags
@@ -88,5 +88,8 @@ e	input.sv	/^module delay_control #(d, e);$/;"	c	module:delay_control
 rega	input.sv	/^  int rega, regb, regr;$/;"	r	module:delay_control
 regb	input.sv	/^  int rega, regb, regr;$/;"	r	module:delay_control
 regr	input.sv	/^  int rega, regb, regr;$/;"	r	module:delay_control
-rega	input.sv	/^    #d rega = regb; \/\/ d is defined as a parameter  FIXME$/;"	r	module:delay_control
-regr	input.sv	/^    #regr regr = regr + 1; \/\/ delay is the value in regr  FIXME$/;"	r	module:delay_control
+delay_control_wire	input.sv	/^module delay_control_wire #(d, e);$/;"	m
+d	input.sv	/^module delay_control_wire #(d, e);$/;"	c	module:delay_control_wire
+e	input.sv	/^module delay_control_wire #(d, e);$/;"	c	module:delay_control_wire
+w$ire	input.sv	/^  wire w$ire, wire$;  \/\/ '$' included$/;"	n	module:delay_control_wire
+wire$	input.sv	/^  wire w$ire, wire$;  \/\/ '$' included$/;"	n	module:delay_control_wire
diff --git a/Units/parser-verilog.r/systemverilog-net-var.d/input.sv b/Units/parser-verilog.r/systemverilog-net-var.d/input.sv
@@ -165,8 +165,17 @@ module delay_control #(d, e);
   int rega, regb, regr;
   initial begin
     #10 rega = regb;
-    #d rega = regb; // d is defined as a parameter  FIXME
+    #d rega = regb; // d is defined as a parameter
     #((d+e)/2) rega = regb; // delay is average of d and e
-    #regr regr = regr + 1; // delay is the value in regr  FIXME
+    #regr regr = regr + 1; // delay is the value in regr
   end
 endmodule
+
+// 10.3 Continuous assignments
+module delay_control_wire #(d, e);
+  wire wirea #10 = wireb;
+  wire wireb #d = wireb;
+  wire wirec #((d+e)/2) = wireb;
+  wire wired #wirer = wirer + 1;
+  wire w$ire, wire$;  // '$' included
+endmodule
diff --git a/Units/parser-verilog.r/verilog-github624.d/expected.tags b/Units/parser-verilog.r/verilog-github624.d/expected.tags
@@ -1 +1 @@
-0	input.v	/^function�::0$/;"	f
+function	input.v	/^function�::0$/;"	f