Merge pull request #2750 from hirooih/sv-misc

SystemVerilog: Misc Fixes

Units/parser-verilog.r/systemverilog-class.d/expected.tags

@@ -118,3 +118,22 @@ set_priority	input.sv	/^  pure virtual function void set_priority (foo::bar x);$
 D.set_priority	input.sv	/^  pure virtual function void set_priority (foo::bar x);$/;"	Q	class:D
 x	input.sv	/^  pure virtual function void set_priority (foo::bar x);$/;"	p	prototype:D.set_priority
 D.set_priority.x	input.sv	/^  pure virtual function void set_priority (foo::bar x);$/;"	p	prototype:D.set_priority
+BasePacket	input.sv	/^virtual class BasePacket;$/;"	C
+send	input.sv	/^pure virtual function integer send(bit[31:0] data); \/\/ No implementation$/;"	Q	class:BasePacket
+BasePacket.send	input.sv	/^pure virtual function integer send(bit[31:0] data); \/\/ No implementation$/;"	Q	class:BasePacket
+data	input.sv	/^pure virtual function integer send(bit[31:0] data); \/\/ No implementation$/;"	p	prototype:BasePacket.send
+BasePacket.send.data	input.sv	/^pure virtual function integer send(bit[31:0] data); \/\/ No implementation$/;"	p	prototype:BasePacket.send
+complex_class	input.sv	/^virtual class static complex_class #(type BASE1=foo, type BASE2=bar) extends base (a, b) impleme/;"	C	inherits:base
+BASE1	input.sv	/^virtual class static complex_class #(type BASE1=foo, type BASE2=bar) extends base (a, b) impleme/;"	c	class:complex_class
+complex_class.BASE1	input.sv	/^virtual class static complex_class #(type BASE1=foo, type BASE2=bar) extends base (a, b) impleme/;"	c	class:complex_class
+BASE2	input.sv	/^virtual class static complex_class #(type BASE1=foo, type BASE2=bar) extends base (a, b) impleme/;"	c	class:complex_class
+complex_class.BASE2	input.sv	/^virtual class static complex_class #(type BASE1=foo, type BASE2=bar) extends base (a, b) impleme/;"	c	class:complex_class
+packet_c	input.sv	/^  Packet packet_c;$/;"	r	class:complex_class
+complex_class.packet_c	input.sv	/^  Packet packet_c;$/;"	r	class:complex_class
+next	input.sv	/^  LinkedPacket next;$/;"	r	class:complex_class
+complex_class.next	input.sv	/^  LinkedPacket next;$/;"	r	class:complex_class
+get_next	input.sv	/^  function LinkedPacket get_next();$/;"	f	class:complex_class
+complex_class.get_next	input.sv	/^  function LinkedPacket get_next();$/;"	f	class:complex_class
+auto_class	input.sv	/^class automatic auto_class;$/;"	C
+a	input.sv	/^  logic a;$/;"	r	class:auto_class
+auto_class.a	input.sv	/^  logic a;$/;"	r	class:auto_class

Units/parser-verilog.r/systemverilog-class.d/input.sv

@@ -73,3 +73,21 @@ class D;
   // UVM-1.2: src/base/uvm_callback.svh
   pure virtual function void set_priority (foo::bar x);
 endclass
+
+// 8.21 Abstract classes and pure virtual methods
+virtual class BasePacket;
+pure virtual function integer send(bit[31:0] data); // No implementation
+endclass
+
+// original complex class
+virtual class static complex_class #(type BASE1=foo, type BASE2=bar) extends base (a, b) implements xxx, yyy;
+  Packet packet_c;
+  LinkedPacket next;
+  function LinkedPacket get_next();
+    get_next = next;
+  endfunction
+endclass
+
+class automatic auto_class;
+  logic a;
+endclass : auto_class

Units/parser-verilog.r/systemverilog-constraint.d/args.ctags

@@ -1 +1,2 @@
 --sort=no
+--kinds-systemverilog=+Q

Units/parser-verilog.r/systemverilog-constraint.d/expected.tags

@@ -1,21 +1,30 @@
 Bus	input.sv	/^class Bus;$/;"	C
 addr	input.sv	/^  rand bit[15:0] addr;$/;"	r	class:Bus
 data	input.sv	/^  rand bit[31:0] data;$/;"	r	class:Bus
+word_align	input.sv	/^  constraint word_align {addr[1:0] == 2'b0;}$/;"	O	class:Bus
 AddrType	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	T
 low	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	c	typedef:AddrType
 mid	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	c	typedef:AddrType
 high	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	c	typedef:AddrType
 MyBus	input.sv	/^class MyBus extends Bus;$/;"	C
 atype	input.sv	/^  rand AddrType atype;$/;"	r	class:MyBus
+addr_range	input.sv	/^  constraint addr_range$/;"	O	class:MyBus
 exercise_bus	input.sv	/^task exercise_bus (MyBus bus);$/;"	t
 bus	input.sv	/^task exercise_bus (MyBus bus);$/;"	p	task:exercise_bus
 res	input.sv	/^  int res;$/;"	r	task:exercise_bus
 C	input.sv	/^class C;$/;"	C
 x	input.sv	/^  rand int x;$/;"	r	class:C
+proto1	input.sv	/^  constraint proto1;        \/\/ implicit form$/;"	O	class:C
+proto2	input.sv	/^  extern constraint proto2; \/\/ explicit form$/;"	Q	class:C
 D	input.sv	/^virtual class D;$/;"	C
+Test	input.sv	/^  pure constraint Test;$/;"	Q	class:D
 E	input.sv	/^class E;$/;"	C
 a	input.sv	/^  rand byte a[5];$/;"	r	class:E
 b	input.sv	/^  rand byte b;$/;"	r	class:E
 excluded	input.sv	/^  rand byte excluded;$/;"	r	class:E
+u	input.sv	/^  constraint u { unique {b, a[2:3], excluded}; }$/;"	O	class:E
+exclusion	input.sv	/^  constraint exclusion { excluded == 5; }$/;"	O	class:E
 C	input.sv	/^class C;$/;"	C
 A	input.sv	/^  rand byte A[] ;$/;"	r	class:C
+C1	input.sv	/^  constraint C1 { foreach ( A [ i ] ) A[i] inside {2,4,8,16}; }$/;"	O	class:C
+C2	input.sv	/^  constraint C2 { foreach ( A [ j ] ) A[j] > 2 * j; }$/;"	O	class:C

Units/parser-verilog.r/systemverilog-constraint.d/input.sv

@@ -1,7 +1,6 @@
 //
 // LRM 18. Constrained random value generation
 //
-// FIXME: constraint is not tagged yet
 
 // 18.3 Concepts and usage
 class Bus;

Units/parser-verilog.r/systemverilog-net-var.d/expected.tags

@@ -27,13 +27,14 @@ ww	input.sv	/^  wire logic [15:0] ww;$/;"	n	module:Net_declarations
 w1	input.sv	/^  interconnect w1;              \/\/ legal$/;"	n	module:Net_declarations
 w2	input.sv	/^  interconnect [3:0] w2;        \/\/ legal$/;"	n	module:Net_declarations
 w3	input.sv	/^  interconnect [3:0] w3 [1:0];  \/\/ legal$/;"	n	module:Net_declarations
-wT	input.sv	/^  nettype T wT;$/;"	r	module:Net_declarations
+wT	input.sv	/^  nettype T wT;$/;"	N	module:Net_declarations
+wTsum	input.sv	/^  nettype T wTsum with Tsum;$/;"	N	module:Net_declarations
 w1	input.sv	/^  wT w1;$/;"	r	module:Net_declarations
 w2	input.sv	/^  wT w2[8];$/;"	r	module:Net_declarations
 w3	input.sv	/^  wTsum w3;$/;"	r	module:Net_declarations
 w4	input.sv	/^  wTsum w4[8];$/;"	r	module:Net_declarations
 TR	input.sv	/^  typedef real TR[5];$/;"	T	module:Net_declarations
-wTR	input.sv	/^  nettype TR wTR;$/;"	r	module:Net_declarations
+wTR	input.sv	/^  nettype TR wTR;$/;"	N	module:Net_declarations
 w5	input.sv	/^  wTR w5;$/;"	r	module:Net_declarations
 w6	input.sv	/^  wTR w6[8];$/;"	r	module:Net_declarations
 Variable_declarations	input.sv	/^module Variable_declarations;$/;"	m

Units/parser-verilog.r/systemverilog-net-var.d/input.sv

@@ -50,7 +50,7 @@ module Net_declarations;
 
   // 6.7.2 Net declarations with user-defined nettypes
   nettype T wT;
-  //nettype T wTsum with Tsum;  // FIXME: "nettype" and "with" are unsupported
+  nettype T wTsum with Tsum;
   wT w1;
   wT w2[8];
   wTsum w3;

Units/parser-verilog.r/systemverilog-parameter.d/expected.tags

@@ -23,16 +23,16 @@ Fifo	input.sv	/^class Fifo #(type T = logic, int DEPTH = 1) implements PutImp#(T
 T	input.sv	/^class Fifo #(type T = logic, int DEPTH = 1) implements PutImp#(T), GetImp#(T);$/;"	c	class:Fifo	parameter:
 DEPTH	input.sv	/^class Fifo #(type T = logic, int DEPTH = 1) implements PutImp#(T), GetImp#(T);$/;"	c	class:Fifo	parameter:
 myFifo	input.sv	/^  T myFifo[$:DEPTH-1];$/;"	r	class:Fifo
-put	input.sv	/^  virtual function void put(T a); \/\/ FIXME : to be ignored?$/;"	f	class:Fifo
-a	input.sv	/^  virtual function void put(T a); \/\/ FIXME : to be ignored?$/;"	p	function:Fifo.put
-get	input.sv	/^  virtual function T get(); \/\/ FIXME : to be ignored?$/;"	f	class:Fifo
+put	input.sv	/^  virtual function void put(T a);$/;"	f	class:Fifo
+a	input.sv	/^  virtual function void put(T a);$/;"	p	function:Fifo.put
+get	input.sv	/^  virtual function T get();$/;"	f	class:Fifo
 Stack	input.sv	/^class Stack #(type T = logic, int DEPTH = 1) implements PutImp#(T), GetImp#(T);$/;"	C
 T	input.sv	/^class Stack #(type T = logic, int DEPTH = 1) implements PutImp#(T), GetImp#(T);$/;"	c	class:Stack	parameter:
 DEPTH	input.sv	/^class Stack #(type T = logic, int DEPTH = 1) implements PutImp#(T), GetImp#(T);$/;"	c	class:Stack	parameter:
 myFifo	input.sv	/^  T myFifo[$:DEPTH-1];$/;"	r	class:Stack
-put	input.sv	/^  virtual function void put(T a); \/\/ FIXME : to be ignored$/;"	f	class:Stack
-a	input.sv	/^  virtual function void put(T a); \/\/ FIXME : to be ignored$/;"	p	function:Stack.put
-get	input.sv	/^  virtual function T get(); \/\/ FIXME : to be ignored$/;"	f	class:Stack
+put	input.sv	/^  virtual function void put(T a);$/;"	f	class:Stack
+a	input.sv	/^  virtual function void put(T a);$/;"	p	function:Stack.put
+get	input.sv	/^  virtual function T get();$/;"	f	class:Stack
 IntfA	input.sv	/^interface class IntfA #(type T1 = logic);$/;"	l
 T1	input.sv	/^interface class IntfA #(type T1 = logic);$/;"	c	ifclass:IntfA	parameter:
 T2	input.sv	/^  typedef T1[1:0] T2;$/;"	T	ifclass:IntfA

Units/parser-verilog.r/systemverilog-parameter.d/input.sv

@@ -55,20 +55,20 @@ endclass
 
 class Fifo #(type T = logic, int DEPTH = 1) implements PutImp#(T), GetImp#(T);
   T myFifo[$:DEPTH-1];
-  virtual function void put(T a); // FIXME : to be ignored?
+  virtual function void put(T a);
     myFifo.push_back(a);
   endfunction
-  virtual function T get(); // FIXME : to be ignored?
+  virtual function T get();
     get = myFifo.pop_front();
   endfunction
 endclass
 
 class Stack #(type T = logic, int DEPTH = 1) implements PutImp#(T), GetImp#(T);
   T myFifo[$:DEPTH-1];
-  virtual function void put(T a); // FIXME : to be ignored
+  virtual function void put(T a);
     myFifo.push_front(a);
   endfunction
-  virtual function T get(); // FIXME : to be ignored
+  virtual function T get();
     get = myFifo.pop_front();
   endfunction
 endclass

Units/parser-verilog.r/systemverilog-task-function.d/expected.tags

@@ -7,6 +7,25 @@ attr	input.sv	/^  task automatic attr ( (* my_attr *) const ref foo, enum { s0,
 foo	input.sv	/^  task automatic attr ( (* my_attr *) const ref foo, enum { s0, s1 } sel_e );$/;"	p	task:task_func.attr
 sel_e	input.sv	/^  task automatic attr ( (* my_attr *) const ref foo, enum { s0, s1 } sel_e );$/;"	p	task:task_func.attr
 C	input.sv	/^class C;$/;"	C
+M	input.sv	/^module M (output a, input b, c, d);$/;"	m
+a	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+b	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+c	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+d	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+myprint	input.sv	/^  function void myprint (int a);$/;"	f	module:M
+a	input.sv	/^  function void myprint (int a);$/;"	p	function:M.myprint
+x	input.sv	/^    logic x;$/;"	r	function:M.myprint
+N	input.sv	/^module N;$/;"	m
+array_locator	input.sv	/^  function array_locator();$/;"	f	module:N
+SA	input.sv	/^    string SA[10], qs[$];$/;"	r	function:N.array_locator
+qs	input.sv	/^    string SA[10], qs[$];$/;"	r	function:N.array_locator
+IA	input.sv	/^    int IA[int], qi[$];$/;"	r	function:N.array_locator
+qi	input.sv	/^    int IA[int], qi[$];$/;"	r	function:N.array_locator
+array_ordering	input.sv	/^  function array_ordering();$/;"	f	module:N
+c	input.sv	/^    struct { byte red, green, blue; } c [512];$/;"	S	function:N.array_ordering
+red	input.sv	/^    struct { byte red, green, blue; } c [512];$/;"	w	struct:N.array_ordering.c
+green	input.sv	/^    struct { byte red, green, blue; } c [512];$/;"	w	struct:N.array_ordering.c
+blue	input.sv	/^    struct { byte red, green, blue; } c [512];$/;"	w	struct:N.array_ordering.c
 foo	input.sv	/^package foo;$/;"	K
 uvm_object	input.sv	/^  typedef logic uvm_object;$/;"	T	package:foo
 bar	input.sv	/^  function logic bar (uvm_object baz);$/;"	f	package:foo
@@ -29,3 +48,4 @@ sigs	input.sv	/^  function void bind_vitf(virtual wb_if.master sigs);$/;"	p	func
 get	input.sv	/^  function string get(string v);$/;"	f	class:func_test
 v	input.sv	/^  function string get(string v);$/;"	p	function:func_test.get
 get_arg	input.sv	/^  function string get_arg();$/;"	f	class:func_test
+parameterized_task	input.sv	/^  function parameterized_task;$/;"	f	class:func_test

Units/parser-verilog.r/systemverilog-task-function.d/input.sv

@@ -24,6 +24,36 @@ class C;
   typedef class   fwd_type_class;
 endclass
 
+// LRM 13.4.1 Return values and void functions
+module M (output a, input b, c, d);
+  always_comb begin
+    a = b + myfunc1(c, d); // call myfunc1 (defined above) as an expression
+    myprint(a); // call myprint (defined below) as a statement
+  end
+
+  function void myprint (int a);
+    logic x;
+  endfunction
+endmodule
+
+// 7.12 Array manipulation methods
+module N;
+  // 7.12.1 Array locator methods
+  function array_locator();
+    string SA[10], qs[$];
+    int IA[int], qi[$];
+    // Find all items greater than 5
+    qi = IA.find( x ) with ( x > 5 );
+  endfunction
+
+  // 7.12.2 Array ordering methods
+  function array_ordering();
+    struct { byte red, green, blue; } c [512];
+    c.sort with ( item.red );               // sort c using the red field only
+    c.sort( x ) with ( {x.blue, x.green} ); // sort by blue then green
+  endfunction
+endmodule
+
 // from UVM-1.2
 package foo;
   import "DPI-C" context function int import_func (string str);
@@ -65,4 +95,11 @@ class func_test;
 
   function string get_arg();
   endfunction
+
+  // cf. LRM 13.8 Parameterized tasks and functions
+  function parameterized_task;
+    // src/reg/uvm_reg_indirect.svh
+    uvm_resource_db#(bit)::set({"REG::", get_full_name()}, "NO_REG_TESTS", 1);
+  endfunction
+
 endclass