Merge pull request #2696 from hirooih/sv-processType

SystemVerilog: introduce processType() for consistent type-handling

Units/parser-verilog.r/systemverilog-basic.d/expected.tags

@@ -81,8 +81,8 @@ ref_test	input.sv	/^function ref_test ($/;"	f	module:mod
 mod.ref_test	input.sv	/^function ref_test ($/;"	f	module:mod
 tref1	input.sv	/^    ref tref1,$/;"	p	function:mod.ref_test
 mod.ref_test.tref1	input.sv	/^    ref tref1,$/;"	p	function:mod.ref_test
-tref2	input.sv	/^    ref wire tref2,$/;"	p	function:mod.ref_test
-mod.ref_test.tref2	input.sv	/^    ref wire tref2,$/;"	p	function:mod.ref_test
+tref2	input.sv	/^    ref wire tref2$/;"	p	function:mod.ref_test
+mod.ref_test.tref2	input.sv	/^    ref wire tref2$/;"	p	function:mod.ref_test
 mynet	input.sv	/^wire [PARAM1-1:0] mynet;$/;"	n	module:mod
 mod.mynet	input.sv	/^wire [PARAM1-1:0] mynet;$/;"	n	module:mod
 gencnt	input.sv	/^genvar gencnt;$/;"	r	module:mod

Units/parser-verilog.r/systemverilog-basic.d/input.sv

@@ -67,7 +67,7 @@ endfunction
 
 function ref_test (
     ref tref1,
-    ref wire tref2,
+    ref wire tref2
     );
 endfunction
 

Units/parser-verilog.r/systemverilog-block.d/expected.tags

@@ -11,11 +11,9 @@ block1	input.sv	/^module block1 #(N_IF = 8) ($/;"	m
 N_IF	input.sv	/^module block1 #(N_IF = 8) ($/;"	c	module:block1	parameter:
 clk	input.sv	/^  input logic clk, rst_n$/;"	p	module:block1
 rst_n	input.sv	/^  input logic clk, rst_n$/;"	p	module:block1
-gi	input.sv	/^  generate for (genvar gi = 0; gi < N_IF; ++gi) begin : b_g1$/;"	r	module:block1
 b_g1	input.sv	/^  generate for (genvar gi = 0; gi < N_IF; ++gi) begin : b_g1$/;"	b	module:block1
 a	input.sv	/^      logic a;$/;"	r	block:block1.b_g1
 var_b_g	input.sv	/^    logic var_b_g;$/;"	r	block:block1.b_g1
-gi	input.sv	/^  for (genvar gi = 0; gi < N_IF; ++gi) begin : b_g2$/;"	r	module:block1
 b_g2	input.sv	/^  for (genvar gi = 0; gi < N_IF; ++gi) begin : b_g2$/;"	b	module:block1
 b1	input.sv	/^    always_comb begin:b1$/;"	b	block:block1.b_g2
 lb1	input.sv	/^        logic lb1;$/;"	r	block:block1.b_g2.b1

Units/parser-verilog.r/systemverilog-checker.d/expected.tags

@@ -55,7 +55,6 @@ in1	input.sv	/^module m(input logic rst, clk, logic en, logic[7:0] in1, in2,$/;"
 in2	input.sv	/^module m(input logic rst, clk, logic en, logic[7:0] in1, in2,$/;"	p	module:m
 in_array	input.sv	/^         in_array [20:0]);$/;"	p	module:m
 v1	input.sv	/^        automatic logic [7:0] v1=0;$/;"	r	module:m
-i	input.sv	/^        for (int i = 0; i < 4; i++) begin$/;"	r	module:m
 counter_model	input.sv	/^checker counter_model(logic flag);$/;"	H
 flag	input.sv	/^checker counter_model(logic flag);$/;"	p	checker:counter_model
 counter	input.sv	/^    bit [2:0] counter = '0;$/;"	r	checker:counter_model

Units/parser-verilog.r/systemverilog-class.d/expected.tags

@@ -107,3 +107,14 @@ randc_logic	input.sv	/^  randc logic           randc_logic;$/;"	r	class:test_att
 test_attributes.randc_logic	input.sv	/^  randc logic           randc_logic;$/;"	r	class:test_attributes
 const_logic	input.sv	/^  const logic           const_logic;$/;"	r	class:test_attributes
 test_attributes.const_logic	input.sv	/^  const logic           const_logic;$/;"	r	class:test_attributes
+D	input.sv	/^class D;$/;"	C
+m_cb_find	input.sv	/^  static function int m_cb_find(foo#(bar) a, callback b);$/;"	f	class:D
+D.m_cb_find	input.sv	/^  static function int m_cb_find(foo#(bar) a, callback b);$/;"	f	class:D
+a	input.sv	/^  static function int m_cb_find(foo#(bar) a, callback b);$/;"	p	function:D.m_cb_find
+D.m_cb_find.a	input.sv	/^  static function int m_cb_find(foo#(bar) a, callback b);$/;"	p	function:D.m_cb_find
+b	input.sv	/^  static function int m_cb_find(foo#(bar) a, callback b);$/;"	p	function:D.m_cb_find
+D.m_cb_find.b	input.sv	/^  static function int m_cb_find(foo#(bar) a, callback b);$/;"	p	function:D.m_cb_find
+set_priority	input.sv	/^  pure virtual function void set_priority (foo::bar x);$/;"	Q	class:D
+D.set_priority	input.sv	/^  pure virtual function void set_priority (foo::bar x);$/;"	Q	class:D
+x	input.sv	/^  pure virtual function void set_priority (foo::bar x);$/;"	p	prototype:D.set_priority
+D.set_priority.x	input.sv	/^  pure virtual function void set_priority (foo::bar x);$/;"	p	prototype:D.set_priority

Units/parser-verilog.r/systemverilog-class.d/input.sv

@@ -64,3 +64,12 @@ class test_attributes;
   randc logic           randc_logic;
   const logic           const_logic;
 endclass : test_attributes
+
+class D;
+  // UVM-1.2: src/base/uvm_callback.svh
+  static function int m_cb_find(foo#(bar) a, callback b);
+    return -1;
+  endfunction
+  // UVM-1.2: src/base/uvm_callback.svh
+  pure virtual function void set_priority (foo::bar x);
+endclass

Units/parser-verilog.r/systemverilog-constraint.d/args.ctags

@@ -0,0 +1 @@
+--sort=no

Units/parser-verilog.r/systemverilog-constraint.d/expected.tags

@@ -0,0 +1,21 @@
+Bus	input.sv	/^class Bus;$/;"	C
+addr	input.sv	/^  rand bit[15:0] addr;$/;"	r	class:Bus
+data	input.sv	/^  rand bit[31:0] data;$/;"	r	class:Bus
+AddrType	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	T
+high	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	c	typedef:AddrType
+mid	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	c	typedef:AddrType
+low	input.sv	/^typedef enum {low, mid, high} AddrType;$/;"	c	typedef:AddrType
+MyBus	input.sv	/^class MyBus extends Bus;$/;"	C
+atype	input.sv	/^  rand AddrType atype;$/;"	r	class:MyBus
+exercise_bus	input.sv	/^task exercise_bus (MyBus bus);$/;"	t
+bus	input.sv	/^task exercise_bus (MyBus bus);$/;"	p	task:exercise_bus
+res	input.sv	/^  int res;$/;"	r	task:exercise_bus
+C	input.sv	/^class C;$/;"	C
+x	input.sv	/^  rand int x;$/;"	r	class:C
+D	input.sv	/^virtual class D;$/;"	C
+E	input.sv	/^class E;$/;"	C
+a	input.sv	/^  rand byte a[5];$/;"	r	class:E
+b	input.sv	/^  rand byte b;$/;"	r	class:E
+excluded	input.sv	/^  rand byte excluded;$/;"	r	class:E
+C	input.sv	/^class C;$/;"	C
+A	input.sv	/^  rand byte A[] ;$/;"	r	class:C

Units/parser-verilog.r/systemverilog-constraint.d/input.sv

@@ -0,0 +1,66 @@
+//
+// LRM 18. Constrained random value generation
+//
+// FIXME: constraint is not tagged yet
+
+// 18.3 Concepts and usage
+class Bus;
+  rand bit[15:0] addr;
+  rand bit[31:0] data;
+  constraint word_align {addr[1:0] == 2'b0;}
+endclass
+
+typedef enum {low, mid, high} AddrType;
+class MyBus extends Bus;
+  rand AddrType atype;
+  constraint addr_range
+  {
+    (atype == low ) -> addr inside { [0 : 15] };
+    (atype == mid ) -> addr inside { [16 : 127]};
+    (atype == high) -> addr inside {[128 : 255]};
+  }
+endclass
+
+task exercise_bus (MyBus bus);
+  int res;
+  // EXAMPLE 1: restrict to low addresses
+  res = bus.randomize() with {atype == low;};
+  // EXAMPLE 2: restrict to address between 10 and 20
+  res = bus.randomize() with {10 <= addr && addr <= 20;};
+  // EXAMPLE 3: restrict data values to powers-of-two
+  res = bus.randomize() with {(data & (data - 1)) == 0;};
+endtask
+
+// 18.5 Constraint blocks
+// 18.5.1 External constraint blocks
+class C;
+  rand int x;
+  constraint proto1;        // implicit form
+  extern constraint proto2; // explicit form
+endclass
+
+// 18.5.2 Constraint inheritance
+virtual class D;
+  pure constraint Test;
+endclass
+
+class E;
+  // 18.5.4 Distribution
+  x != 200;
+  x dist {100 := 1, 200 := 2, 300 := 5}
+
+  // 18.5.5 Uniqueness constraints
+  rand byte a[5];
+  rand byte b;
+  rand byte excluded;
+  constraint u { unique {b, a[2:3], excluded}; }
+  constraint exclusion { excluded == 5; }
+endclass
+
+// 18.5.8 Iterative constraints
+// 18.5.8.1 foreach iterative constraints
+class C;
+  rand byte A[] ;
+  constraint C1 { foreach ( A [ i ] ) A[i] inside {2,4,8,16}; }
+  constraint C2 { foreach ( A [ j ] ) A[j] > 2 * j; }
+endclass

Units/parser-verilog.r/systemverilog-covergroup.d/expected.tags

@@ -17,4 +17,5 @@ deferred_cover2	input.sv	/^    deferred_cover2     : cover final () task();$/;"
 test.deferred_cover2	input.sv	/^    deferred_cover2     : cover final () task();$/;"	A	covergroup:test
 deferred_assume2	input.sv	/^    deferred_assume2    : assume final () task();$/;"	A	covergroup:test
 test.deferred_assume2	input.sv	/^    deferred_assume2    : assume final () task();$/;"	A	covergroup:test
+cg	input.sv	/^covergroup cg @@ ( begin task_end );$/;"	V
 var_to_check_context	input.sv	/^reg var_to_check_context;$/;"	r

Units/parser-verilog.r/systemverilog-covergroup.d/input.sv

@@ -10,4 +10,7 @@ covergroup test;
     deferred_assume2    : assume final () task();
 endgroup
 
+covergroup cg @@ ( begin task_end );
+endgroup
+
 reg var_to_check_context;

Units/parser-verilog.r/systemverilog-directive.d/expected.tags

@@ -42,6 +42,7 @@ BAR	input.sv	/^`define BAR$/;"	c	module:define_in_port
 c1	input.sv	/^        input logic c1,$/;"	p	module:define_in_port
 d2	input.sv	/^        input logic d2,$/;"	p	module:define_in_port
 c3	input.sv	/^        input logic c3$/;"	p	module:define_in_port
+MY_DEFINE	input.sv	/^`define MY_DEFINE$/;"	c
 assert_clk	input.sv	/^`define assert_clk(arg, __clk=clk, __rst_n=rst_n) \\$/;"	c
 forSkipMacro	input.sv	/^module forSkipMacro;$/;"	m
 add_t	input.sv	/^`define add_t(f) f``_t$/;"	c	module:forSkipMacro

Units/parser-verilog.r/systemverilog-directive.d/input.sv

@@ -195,10 +195,19 @@ module define_in_port (
 
 endmodule
 
+`undef  MY_UNDEF
+`define MY_DEFINE
+
 `define assert_clk(arg, __clk=clk, __rst_n=rst_n) \
  assert property (@(posedge __clk) disable iff (!__rst_n) arg) 
 
 module forSkipMacro;
 `define add_t(f) f``_t
     var `add_t(foo) = '0;
+
+    `macro({e},FOO)
+    `macro("string",FOO)
+    `macro(bar)
+    `macro(int)
+    `macro(int,bar)
 endmodule

Units/parser-verilog.r/systemverilog-module.d/args.ctags

@@ -0,0 +1 @@
+--sort=no

Units/parser-verilog.r/systemverilog-module.d/expected.tags

@@ -0,0 +1,14 @@
+apb_if	input.sv	/^typedef logic apb_if;$/;"	T
+blk_dut1	input.sv	/^module blk_dut1 (input apb_if    apb, input bit rst); $/;"	m
+apb	input.sv	/^module blk_dut1 (input apb_if    apb, input bit rst); $/;"	p	module:blk_dut1
+rst	input.sv	/^module blk_dut1 (input apb_if    apb, input bit rst); $/;"	p	module:blk_dut1
+blk_dut2	input.sv	/^module blk_dut2 (apb_if    apb, input bit rst);$/;"	m
+apb	input.sv	/^module blk_dut2 (apb_if    apb, input bit rst);$/;"	r	module:blk_dut2
+rst	input.sv	/^module blk_dut2 (apb_if    apb, input bit rst);$/;"	r	module:blk_dut2
+blk_dut3	input.sv	/^module blk_dut3 (logic    apb, input bit rst);$/;"	m
+apb	input.sv	/^module blk_dut3 (logic    apb, input bit rst);$/;"	r	module:blk_dut3
+rst	input.sv	/^module blk_dut3 (logic    apb, input bit rst);$/;"	r	module:blk_dut3
+blk_dut4	input.sv	/^module blk_dut4 #(int BASE_ADDR='h0) (apb_if    apb,$/;"	m
+BASE_ADDR	input.sv	/^module blk_dut4 #(int BASE_ADDR='h0) (apb_if    apb,$/;"	c	module:blk_dut4
+apb	input.sv	/^module blk_dut4 #(int BASE_ADDR='h0) (apb_if    apb,$/;"	r	module:blk_dut4
+rst	input.sv	/^                                     input bit rst);$/;"	r	module:blk_dut4

Units/parser-verilog.r/systemverilog-module.d/input.sv

@@ -0,0 +1,12 @@
+// user defined type port
+typedef logic apb_if;
+module blk_dut1 (input apb_if    apb, input bit rst); 
+endmodule
+// FIXME: first port has no direction
+module blk_dut2 (apb_if    apb, input bit rst);
+endmodule
+module blk_dut3 (logic    apb, input bit rst);
+endmodule
+module blk_dut4 #(int BASE_ADDR='h0) (apb_if    apb,
+                                     input bit rst);
+endmodule

Units/parser-verilog.r/systemverilog-net-var.d/expected.tags

@@ -10,10 +10,11 @@ top	input.sv	/^module top();$/;"	m
 iBus	input.sv	/^  interconnect [0:1] iBus;$/;"	n	module:top
 rlMod	input.sv	/^module rlMod(input interconnect [0:1] iBus);$/;"	m
 iBus	input.sv	/^module rlMod(input interconnect [0:1] iBus);$/;"	p	module:rlMod
-Net_declarations	input.sv	/^module Net_declarations$/;"	m
+Net_declarations	input.sv	/^module Net_declarations;$/;"	m
+cap1	input.sv	/^  trireg (large) logic #(0,0,0) cap1;$/;"	n	module:Net_declarations
 addressT	input.sv	/^  typedef logic [31:0] addressT;$/;"	T	module:Net_declarations
-ecc	input.sv	/^  wire struct packed { logic ecc; logic [7:0] data; } memsig; \/\/ FIXME: ignored -> memsig$/;"	r	module:Net_declarations
-data	input.sv	/^  wire struct packed { logic ecc; logic [7:0] data; } memsig; \/\/ FIXME: ignored -> memsig$/;"	r	module:Net_declarations
+w1	input.sv	/^  wire addressT w1;$/;"	n	module:Net_declarations
+memsig	input.sv	/^  wire struct packed { logic ecc; logic [7:0] data; } memsig;$/;"	n	module:Net_declarations
 w	input.sv	/^  wire w; \/\/ equivalent to "wire logic w;"$/;"	n	module:Net_declarations
 w	input.sv	/^  wire logic w;$/;"	n	module:Net_declarations
 ww	input.sv	/^  wire [15:0] ww; \/\/ equivalent to "wire logic [15:0] ww;"$/;"	n	module:Net_declarations
@@ -22,6 +23,7 @@ w1	input.sv	/^  interconnect w1;              \/\/ legal$/;"	n	module:Net_declar
 w2	input.sv	/^  interconnect [3:0] w2;        \/\/ legal$/;"	n	module:Net_declarations
 w3	input.sv	/^  interconnect [3:0] w3 [1:0];  \/\/ legal$/;"	n	module:Net_declarations
 wT	input.sv	/^  nettype T wT;$/;"	r	module:Net_declarations
+Tsum	input.sv	/^  nettype T wTsum with Tsum;  \/\/ FIXME: $/;"	r	module:Net_declarations
 w1	input.sv	/^  wT w1;$/;"	r	module:Net_declarations
 w2	input.sv	/^  wT w2[8];$/;"	r	module:Net_declarations
 w3	input.sv	/^  wTsum w3;$/;"	r	module:Net_declarations
@@ -35,6 +37,7 @@ s1	input.sv	/^  shortint s1, s2[0:9];$/;"	r	module:Variable_declarations
 s2	input.sv	/^  shortint s1, s2[0:9];$/;"	r	module:Variable_declarations
 v	input.sv	/^  var v; \/\/ equivalent to "var logic v;"$/;"	r	module:Variable_declarations
 vw	input.sv	/^  var [15:0] vw; \/\/ equivalent to "var logic [15:0] vw;"$/;"	r	module:Variable_declarations
+status	input.sv	/^  var enum bit { clear, error } status;$/;"	r	module:Variable_declarations
 data_in	input.sv	/^  input var logic data_in;$/;"	p	module:Variable_declarations
 r	input.sv	/^  var reg r;$/;"	r	module:Variable_declarations
 i	input.sv	/^  int i = 0;$/;"	r	module:Variable_declarations
@@ -82,6 +85,54 @@ sub	input.sv	/^module sub(intf_i p);$/;"	m
 p	input.sv	/^module sub(intf_i p);$/;"	r	module:sub
 data	input.sv	/^  my_data_t data;$/;"	r	module:sub
 user_define_types_1	input.sv	/^module user_define_types_1;$/;"	m
+enum_test	input.sv	/^module enum_test;$/;"	m
+light1	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	E	module:enum_test
+green	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	c	enum:enum_test.light1
+yellow	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	c	enum:enum_test.light1
+red	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	c	enum:enum_test.light1
+light2	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	E	module:enum_test
+green	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	c	enum:enum_test.light2
+yellow	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	c	enum:enum_test.light2
+red	input.sv	/^  enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;"	c	enum:enum_test.light2
+state	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	E	module:enum_test
+S2	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.state
+S1	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.state
+XX	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.state
+IDLE	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.state
+next	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	E	module:enum_test
+S2	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.next
+S1	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.next
+XX	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.next
+IDLE	input.sv	/^  enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;"	c	enum:enum_test.next
+medal	input.sv	/^  enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;"	E	module:enum_test
+gold	input.sv	/^  enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;"	c	enum:enum_test.medal
+silver	input.sv	/^  enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;"	c	enum:enum_test.medal
+bronze	input.sv	/^  enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;"	c	enum:enum_test.medal
+medal2	input.sv	/^  enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;"	E	module:enum_test
+gold	input.sv	/^  enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;"	c	enum:enum_test.medal2
+silver	input.sv	/^  enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;"	c	enum:enum_test.medal2
+bronze	input.sv	/^  enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;"	c	enum:enum_test.medal2
+medal3	input.sv	/^  enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;"	E	module:enum_test
+gold	input.sv	/^  enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;"	c	enum:enum_test.medal3
+silver	input.sv	/^  enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;"	c	enum:enum_test.medal3
+bronze	input.sv	/^  enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;"	c	enum:enum_test.medal3
+boolean	input.sv	/^  typedef enum {NO, YES} boolean;$/;"	T	module:enum_test
+YES	input.sv	/^  typedef enum {NO, YES} boolean;$/;"	c	typedef:enum_test.boolean
+NO	input.sv	/^  typedef enum {NO, YES} boolean;$/;"	c	typedef:enum_test.boolean
+myvar	input.sv	/^  boolean myvar; \/\/ named type$/;"	r	module:enum_test
+E1	input.sv	/^  typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;"	T	module:enum_test
+jmp	input.sv	/^  typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;"	c	typedef:enum_test.E1
+sub	input.sv	/^  typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;"	c	typedef:enum_test.E1
+add	input.sv	/^  typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;"	c	typedef:enum_test.E1
+vr	input.sv	/^  enum { register[2] = 1, register[2:4] = 10 } vr; \/\/ FIXME$/;"	E	module:enum_test
+register	input.sv	/^  enum { register[2] = 1, register[2:4] = 10 } vr; \/\/ FIXME$/;"	c	enum:enum_test.vr
+register	input.sv	/^  enum { register[2] = 1, register[2:4] = 10 } vr; \/\/ FIXME$/;"	c	enum:enum_test.vr
+cmplx_enum1	input.sv	/^  enum logic signed [3:0] { foo, bar } [1:0] cmplx_enum1; $/;"	E	module:enum_test
+bar	input.sv	/^  enum logic signed [3:0] { foo, bar } [1:0] cmplx_enum1; $/;"	c	enum:enum_test.cmplx_enum1
+foo	input.sv	/^  enum logic signed [3:0] { foo, bar } [1:0] cmplx_enum1; $/;"	c	enum:enum_test.cmplx_enum1
+cmplx_enum2	input.sv	/^  enum logic unsigned [3:0] { foo, bar } [] cmplx_enum2; $/;"	E	module:enum_test
+bar	input.sv	/^  enum logic unsigned [3:0] { foo, bar } [] cmplx_enum2; $/;"	c	enum:enum_test.cmplx_enum2
+foo	input.sv	/^  enum logic unsigned [3:0] { foo, bar } [] cmplx_enum2; $/;"	c	enum:enum_test.cmplx_enum2
 delay_control	input.sv	/^module delay_control #(d, e);$/;"	m
 d	input.sv	/^module delay_control #(d, e);$/;"	c	module:delay_control
 e	input.sv	/^module delay_control #(d, e);$/;"	c	module:delay_control
@@ -91,5 +142,11 @@ regr	input.sv	/^  int rega, regb, regr;$/;"	r	module:delay_control
 delay_control_wire	input.sv	/^module delay_control_wire #(d, e);$/;"	m
 d	input.sv	/^module delay_control_wire #(d, e);$/;"	c	module:delay_control_wire
 e	input.sv	/^module delay_control_wire #(d, e);$/;"	c	module:delay_control_wire
+wirea	input.sv	/^  wire wirea #10 = wireb;$/;"	n	module:delay_control_wire
+wireb	input.sv	/^  wire wireb #d = wireb;$/;"	n	module:delay_control_wire
+wirec	input.sv	/^  wire wirec #((d+e)\/2) = wireb;$/;"	n	module:delay_control_wire
+wired	input.sv	/^  wire wired #wirer = wirer + 1;$/;"	n	module:delay_control_wire
 w$ire	input.sv	/^  wire w$ire, wire$;  \/\/ '$' included$/;"	n	module:delay_control_wire
 wire$	input.sv	/^  wire w$ire, wire$;  \/\/ '$' included$/;"	n	module:delay_control_wire
+rst	input.sv	/^module rst;$/;"	m
+trst_n	input.sv	/^  logic trst_n;$/;"	r	module:rst