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Merge pull request #3722 from hirooih/verilog-text-macro-as-an-identi…
…fier verilog: treat a text-macro as an identifier
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--sort=no |
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Units/parser-verilog.r/systemverilog-github3712.d/expected.tags
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XXX_TOP input.sv /^`define XXX_TOP foo_top$/;" d | ||
XXX input.sv /^`define XXX foo$/;" d | ||
`XXX input.sv /^module `XXX ();$/;" m | ||
add_t input.sv /^`define add_t(f) f``_t$/;" d module:`XXX | ||
`XXX_TOP input.sv /^module `XXX_TOP();$/;" m | ||
foo input.sv /^class foo;$/;" C | ||
new input.sv /^ function new(string name="...");$/;" f class:foo | ||
name input.sv /^ function new(string name="...");$/;" p function:foo.new | ||
`add_t input.sv /^ var `add_t(foo) = '0;$/;" r class:foo |
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Units/parser-verilog.r/systemverilog-github3712.d/input.sv
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// https://github.com/universal-ctags/ctags/issues/3712 | ||
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`define XXX_TOP foo_top | ||
`define XXX foo | ||
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module `XXX (); | ||
`define add_t(f) f``_t | ||
endmodule | ||
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module `XXX_TOP(); | ||
`XXX U_XXX (); // cannot be detected | ||
endmodule | ||
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class foo; | ||
// from a design pattern in UVM | ||
`xxx_begin(bar) // must be ignored | ||
`xxx_end // must be ignored | ||
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function new(string name="..."); | ||
super.new(name); | ||
endfunction : new | ||
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// from systemverilog-directive.d | ||
var `add_t(foo) = '0; | ||
endclass : foo |
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