verilog does not recognize that the module name is a macro definition

[zhujianhua0]

The name of the parser:
verilog

The command line you used to run ctags:

any

The content of input file:

module `XXX

The tags output you are not satisfied with:

The tags output you expect:

The version of ctags:

How do you get ctags binary:

(
github
)

[hirooih]

This is a known issue.

#2674, #2675

Only `define directive emits a tag. All other directives skip the whole line included.

You may don't want to expand macros in your parser.

No, I don't. If we need to expand macros, I prefer to use external preprocessor and use LINE and FILE directive.

@zhujianhua0

The tags output you expect:

What do you expect?

[zhujianhua0]

This is a known issue.

#2674, #2675

Only `define directive emits a tag. All other directives skip the whole line included.

You may don't want to expand macros in your parser.

No, I don't. If we need to expand macros, I prefer to use external preprocessor and use LINE and FILE directive.

@zhujianhua0

The tags output you expect:

What do you expect?

I expect output have kind of module
`XXX xxx.v .... kind:module

vscode verilog extensions use ctags to instance module, when module name is macro , can't find 'kind:module' in tags，extension not working

[hirooih]

`XXX xxx.v .... kind:module

I don't this this works for you.

How `xxx is defined in your design?
It should be defined as name of a module. For example:

`define xxx foo

In this case tag output should be something like:

foo foo.v .... kind:module

Or xxx may be overridden as 'bar' by command line option.
In this case tag output should be something like:

bar bar.v .... kind:module

[zhujianhua0]

`XXX xxx.v .... kind:module

I don't this this works for you.

How `xxx is defined in your design? It should be defined as name of a module. For example:

`define xxx foo

In this case tag output should be something like:

foo foo.v .... kind:module

Or xxx may be overridden as 'bar' by command line option. In this case tag output should be something like:

bar bar.v .... kind:module

An ip will have multiple sets of macro definition configurations in the system, the same module name is not allowed to have different functions, we define the module name with a macro, so that different configurations will be modified into different module names, module instantiation also needs Instantiate using macro definition, so I want to get the original macro definition name, not the defined value

`XXX is a sub module
foo_define.v

`define XXX_TOP  foo_top
`define XXX          foo 

xxx.v

module `XXX (
)

xxx_top.v

module `XXX_TOP
...
`XXX U_XXX (      //when i use vscode verilog extensions to instance xxx.v，this shoud be `XXX ,not foo 
)

[masatake]

Interesting discussion.

I have not had a chance to use SystemVerilog, but I found another reason to extract `XXX:

/tmp/input.sv:

module `XXX;

program mod_prog1;
endprogram : mod_prog1

endmodule

$ ./ctags --options=NONE -o - /tmp/foo.sv
./ctags --options=NONE -o - /tmp/foo.sv
ctags: Notice: No options will be read from files or environment
/tmp/foo.sv:6:parsers/verilog.c:963:Internal Error:Unexpected current context 
mod_prog1	/tmp/foo.sv	/^program mod_prog1;$/;"	P

ctags could not fill the scope field of mod_prog1.
ctags reported an internal error.

If the parser accepts `XXX, ctags can fill the scope field without reporting the internal error.

[hirooih]

@zhujianhua0

I understood your request.

You should use the configuration feature of the current Verilog (SystemVerilog) for this case.
But we don't support preprocessor now. I find that nothing wrong with treating a text-macro as an identifier.

The basic fix for parsers/verilog.c is simply:

@@ -887,7 +887,7 @@ static bool isIdentifier (tokenInfo* token)
                        int c = vStringChar (token->name, i);
                        if (i == 0)
                        {
-                               if (c == '`' || !isWordToken (c))
+                               if (!isWordToken (c))
                                        return false;
                        }
                        else

I have noticed that this modification exposes a hidden bug. I have to fix it before fixing this.
Give me some days.

[hirooih]

@zhujianhua0

PR #3722 fixes this. It was merged into master.

Thank you for your report.