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SystemVerilog: support property:parameter (update for #2537) #2666

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Oct 22, 2020

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  1. SystemVerilog: parameter property support (part 2)

    Implements LRM 6.20.1 rule
    - If the declaration of a design element uses a parameter_port_list (even an empty one),
      then in any parameter_declaration directly contained within the declaration,
      the parameter keyword shall be a synonym for the localparam keyword (see 6.20.4).
    - All param_assignments appearing within a class body shall become localparam declarations
      regardless of the presence or absence of a parameter_port_list.
    - All param_assignments appearing within a generate block, package, or compilation-unit scope
      shall become localparam declarations.
    
    Only "generate block" rule is not implemented yet, because it does not create a context.
    hirooih committed Oct 21, 2020
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