SystemVerilog: exit loop on EOF

[hirooih]

There were 8 bugs which cause infinite loop due to lack of EOF check.
While checking loops, loops which can be refactored were found and fixed.

I do not add test cases for this issue, because we need a unit case for each loop.

[coveralls]

Coverage remained the same at 86.927% when pulling 54b431e on hirooih:sv-eof-on-loop into 4f69a72 on universal-ctags:master.

[codecov]

Codecov Report

Merging #2733 (54b431e) into master (4f69a72) will decrease coverage by 0.00%.
The diff coverage is 100.00%.

@@            Coverage Diff             @@
##           master    #2733      +/-   ##
==========================================
- Coverage   86.83%   86.83%   -0.01%     
==========================================
  Files         189      189              
  Lines       40251    40250       -1     
==========================================
- Hits        34953    34952       -1     
  Misses       5298     5298              

Impacted Files	Coverage Δ
parsers/verilog.c	98.17% <100.00%> (-0.01%)	⬇️

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