Verilog: fix for continuous assignment delays #3786
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FIx to support the following code. ``` wire universal-ctags#10 wireA; wire universal-ctags#10 wirea = wireb; ``` cf. LRM 10.3.3 Continuous assignment delays Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
Codecov ReportPatch coverage:
Additional details and impacted files@@ Coverage Diff @@
## master #3786 +/- ##
==========================================
+ Coverage 83.01% 83.05% +0.03%
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Files 227 227
Lines 55126 55201 +75
==========================================
+ Hits 45764 45845 +81
+ Misses 9362 9356 -6
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FIx to support the following code.
cf. LRM 10.3.3 Continuous assignment delays