Soapy: Change time interval in AXI DMAC checks

Soapy: Add timeouts to AXI IIC transactions Soapy: Fix AXI IIC race conditions and add workaround for IP Core bugs Soapy: Disable AXI IIC GPOs Soapy: Allow zero-length IIC transactions for address probing Soapy: Fix register access before access control function setup in RF TS and I2S cores Soapy: Fix IRQ controller being deleted before DMACs Soapy: Add bool aliases to GPIO methods Soapy: Add I2C bus scanning Soapy: Add I2C bus for expansion board Soapy: Add Si5351 library Soapy: Add initClocks implementation Soapy: Add AXI PCIe library Soapy: Add AD9361 library (untested) Soapy: Add DMA Buffer allocation Soapy: Misc changes Signed-off-by: João Silva <jgc3silva@gmail.com>
vankxr · Nov 13, 2023 · bffdaf4 · bffdaf4
1 parent 68e9f74
commit bffdaf4
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Showing 27 changed files with 12,155 additions and 487 deletions.
diff --git a/software/soapy/src/AD9361.cpp b/software/soapy/src/AD9361.cpp
diff --git a/software/soapy/src/AXIDMAC.cpp b/software/soapy/src/AXIDMAC.cpp
@@ -108,22 +108,26 @@ AXIDMAC::AXIDMAC(void *base_address, AXIDMAC::IRQConfig irq_config): AXIPeripher
 }
 AXIDMAC::~AXIDMAC()
 {
-    if(this->irq_config.controller)
+    if(this->irq_config.controller != nullptr)
+    {
+        this->irq_config.controller->setISR(this->irq_config.irq, nullptr);
         this->irq_config.controller->setIRQEnabled(this->irq_config.irq, false);
+    }
 }
 
 void AXIDMAC::init(AXIDMAC::IRQConfig irq_config)
 {
     if(this->irq_config.controller != nullptr)
         throw std::runtime_error("AXI DMAC: Already initialized");
 
-    if(irq_config.controller == nullptr)
+    if(irq_config.controller == nullptr) // Current implementation requires IRQ support
         return;
 
     this->irq_config = irq_config;
 
     this->irq_config.controller->setISR(this->irq_config.irq, AXIDMAC::ISR, static_cast<void *>(this));
     this->irq_config.controller->setIRQEnabled(this->irq_config.irq, true);
+    this->irq_config.controller->setIRQPending(this->irq_config.irq, false);
 
     this->writeReg(AXI_DMAC_REG_IRQ_MASK, AXI_DMAC_REG_IRQ_x_IRQ_XFER_QUEUED); // Mask only the transfer queued IRQ
 }
@@ -276,10 +280,10 @@ void AXIDMAC::waitTransferCompletion(uint8_t id, uint32_t timeout_ms)
 
     AXIDMAC::Transfer *xfer = &this->transfers[id];
 
-    uint64_t timeout_us = (uint64_t)timeout_ms * 1000ULL;
+    uint64_t timeout = (uint64_t)timeout_ms * 10ULL;
 
-    while(--timeout_us && !xfer->done)
-        usleep(1);
+    while(--timeout && !xfer->done)
+        usleep(100);
 
     if(!xfer->done)
         throw std::runtime_error("AXI DMAC: Timed out waiting for transfer " + std::to_string(id));

diff --git a/software/soapy/src/AXII2S.cpp b/software/soapy/src/AXII2S.cpp
@@ -2,17 +2,24 @@
 
 AXII2S::AXII2S(void *base_address, std::function<bool()> access_allowed_fn): AXIPeripheral(base_address)
 {
-    uint32_t version = this->getIPVersion();
-
-    if(AXI_CORE_VERSION_MAJOR(version) < 1)
-        throw std::runtime_error("AXI I2S Core v" + std::to_string(AXI_CORE_VERSION_MAJOR(version)) + "." + std::to_string(AXI_CORE_VERSION_MINOR(version)) + "." + std::to_string(AXI_CORE_VERSION_PATCH(version)) + " is not supported");
-
     this->init(access_allowed_fn);
 }
 
 void AXII2S::init(std::function<bool()> access_allowed_fn)
 {
+    if(this->access_allowed_fn != nullptr)
+        throw std::runtime_error("AXI RF Timestamping: Already initialized");
+
+    if(access_allowed_fn == nullptr)
+        return;
+
     this->access_allowed_fn = access_allowed_fn;
+
+    uint32_t version = this->getIPVersion();
+
+    if(AXI_CORE_VERSION_MAJOR(version) < 1)
+        throw std::runtime_error("AXI I2S Core v" + std::to_string(AXI_CORE_VERSION_MAJOR(version)) + "." + std::to_string(AXI_CORE_VERSION_MINOR(version)) + "." + std::to_string(AXI_CORE_VERSION_PATCH(version)) + " is not supported");
+
 }
 
 uint32_t AXII2S::getIPVersion()