Merge pull request trishume#12 from manuelgutierrezsigasi/master

Support VHDL and Verilog
varungandhi-src · Nov 26, 2021 · 4b27b5c · 4b27b5c
2 parents 73b9730 + e7649fa
commit 4b27b5c
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diff --git a/assets/default_metadata.packdump b/assets/default_metadata.packdump
diff --git a/assets/default_newlines.packdump b/assets/default_newlines.packdump
diff --git a/assets/default_nonewlines.packdump b/assets/default_nonewlines.packdump
diff --git a/testdata/Packages b/testdata/Packages
+3 −1		README.md
+1 −0		VHDL/SOURCE
+1 −0		VHDL/VERSION
+62 −0		VHDL/vhdl.tmLanguage.sublime-syntax
+1 −0		Verilog/SOURCE
+1 −0		Verilog/VERSION
+73 −0		Verilog/verilog.tmLanguage.sublime-syntax