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Fix panic with explicit clock and implicit reset
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dalance committed Dec 2, 2024
1 parent 569bdf7 commit 1f60656
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Showing 4 changed files with 39 additions and 16 deletions.
35 changes: 20 additions & 15 deletions crates/emitter/src/emitter.rs
Original file line number Diff line number Diff line change
Expand Up @@ -580,6 +580,25 @@ impl Emitter {
}
}

fn always_ff_explicit_event_list(
&mut self,
arg: &AlwaysFfEventList,
decl: &AlwaysFfDeclaration,
) {
self.l_paren(&arg.l_paren);
self.always_ff_clock(&arg.always_ff_clock);
if let Some(ref x) = arg.always_ff_event_list_opt {
if self.always_ff_reset_exist_in_sensitivity_list(&x.always_ff_reset) {
self.comma(&x.comma);
self.space(1);
}
self.always_ff_reset(&x.always_ff_reset);
} else if self.always_ff_if_reset_exists(decl) {
self.always_ff_implicit_reset_event();
}
self.r_paren(&arg.r_paren);
}

fn always_ff_implicit_event_list(&mut self, arg: &AlwaysFfDeclaration) {
self.str("(");
self.always_ff_implicit_clock_event();
Expand Down Expand Up @@ -2303,7 +2322,7 @@ impl VerylWalker for Emitter {
self.str("@");
self.space(1);
if let Some(ref x) = arg.always_ff_declaration_opt {
self.always_ff_event_list(&x.always_ff_event_list);
self.always_ff_explicit_event_list(&x.always_ff_event_list, arg);
} else {
self.always_ff_implicit_event_list(arg);
}
Expand All @@ -2312,20 +2331,6 @@ impl VerylWalker for Emitter {
self.in_always_ff = false;
}

/// Semantic action for non-terminal 'AlwaysFfEventList'
fn always_ff_event_list(&mut self, arg: &AlwaysFfEventList) {
self.l_paren(&arg.l_paren);
self.always_ff_clock(&arg.always_ff_clock);
if let Some(ref x) = arg.always_ff_event_list_opt {
if self.always_ff_reset_exist_in_sensitivity_list(&x.always_ff_reset) {
self.comma(&x.comma);
self.space(1);
}
self.always_ff_reset(&x.always_ff_reset);
}
self.r_paren(&arg.r_paren);
}

/// Semantic action for non-terminal 'AlwaysFfClock'
fn always_ff_clock(&mut self, arg: &AlwaysFfClock) {
if let Ok(found) = symbol_table::resolve(arg.hierarchical_identifier.as_ref()) {
Expand Down
2 changes: 1 addition & 1 deletion testcases/map/testcases/sv/12_always.sv.map

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9 changes: 9 additions & 0 deletions testcases/sv/12_always.sv
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,15 @@ module veryl_testcase_Module12_1 (
);
logic a;
logic b;
logic c;

always_ff @ (posedge i_clk, negedge i_rst_n) begin
if (!i_rst_n) begin
c <= 0;
end else begin
c <= ~a;
end
end

always_ff @ (posedge i_clk, negedge i_rst_n) begin
if (!i_rst_n) begin
Expand Down
9 changes: 9 additions & 0 deletions testcases/veryl/12_always.veryl
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,15 @@ module Module12_1 (
) {
var a: logic;
var b: logic;
var c: logic;

always_ff (i_clk) {
if_reset {
c = 0;
} else {
c = ~a;
}
}

always_ff {
if_reset {
Expand Down

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