Merge remote-tracking branch 'cambridge/upstream-llvm-merge' into pet…

…r/upstream-llvm-merge-2

libcxx/utils/libcxx/test/dsl.py

@@ -69,8 +69,14 @@ def f(config, *args, **kwargs):
             if cacheKey not in cache:
                 cache[cacheKey] = function(config, *args, **kwargs)
                 # Update the persistent cache so it knows about the new key
-                with open(persistentCache, "wb") as cacheFile:
+                # We write to a PID-suffixed file and rename the result to
+                # ensure that the cache is not corrupted when running the test
+                # suite with multiple shards. Since this file is in the same
+                # directory as the destination, os.replace() will be atomic.
+                unique_suffix = ".tmp." + str(os.getpid())
+                with open(persistentCache + unique_suffix, "wb") as cacheFile:
                     pickle.dump(cache, cacheFile)
+                os.replace(persistentCache + unique_suffix, persistentCache)
             return cache[cacheKey]
 
         return f

libunwind/src/Registers.hpp

@@ -4618,7 +4618,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const {
   if ((regNum > 0) && (regNum < 32))
     return _registers[regNum];
   if (regNum == UNW_RISCV_VLENB) {
-    reg_t vlenb;
+    size_t vlenb;
     __asm__("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
   }

libunwind/src/UnwindRegistersRestore.S

@@ -1318,19 +1318,19 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv)
 
 #elif defined(__riscv)
 
-.macro restore_fpr num
+.macro restore_fpr num, ctxreg
 #ifdef __CHERI_PURE_CAPABILITY__
-  cfld   f\num, (__SIZEOF_CHERI_CAPABILITY__ * 32 + 8 * \num)(ca0)
+  cfld   f\num, (RISCV_FOFFSET + RISCV_FSIZE * \num)(c\ctxreg)
 #else
-  FLOAD  f\num, (8 * 32 + 8 * \num)(a0)
+  FLOAD  f\num, (RISCV_FOFFSET + RISCV_FSIZE * \num)(\ctxreg)
 #endif
 .endm
 
-.macro restore_gpr num
+.macro restore_gpr num, ctxreg
 #ifdef __CHERI_PURE_CAPABILITY__
-  clc   c\num, (__SIZEOF_CHERI_CAPABILITY__ * \num)(ca0)
+  clc   c\num, (__SIZEOF_CHERI_CAPABILITY__ * \num)(c\ctxreg)
 #else
-  ILOAD x\num, (8 * \num)(a0)
+  ILOAD x\num, (RISCV_ISIZE * \num)(\ctxreg)
 #endif
 .endm
 
@@ -1344,24 +1344,24 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv)
 DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
 # if defined(__riscv_flen)
   .irp i,FROM_0_TO_31
-    restore_fpr f\i, (RISCV_FOFFSET + RISCV_FSIZE * \i)(a0)
+    restore_fpr \i, a0
   .endr
 # endif
 
 #ifdef __CHERI_PURE_CAPABILITY__
   clc   c1, (__SIZEOF_CHERI_CAPABILITY__ * 0)(ca0) // restore pc into ra
 #else
-  ILOAD    x1, (8 * 0)(a0) // restore pc into ra
+  ILOAD    x1, (RISCV_ISIZE * 0)(a0) // restore pc into ra
 #endif
   // x0 is zero
   .irp i,2,3,4,5,6,7,8,9
-    restore_gpr x\i, (RISCV_ISIZE * \i)(a0)
+    restore_gpr \i, a0
   .endr
   // skip a0 for now
   .irp i,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
-    restore_gpr x\i, (RISCV_ISIZE * \i)(a0)
+    restore_gpr \i, a0
   .endr
-  restore_gpr    x10, (RISCV_ISIZE * 10)(a0)   // restore a0
+  restore_gpr 10, a0  // restore a0
 
 #ifdef __CHERI_PURE_CAPABILITY__
   cret          // jump to cra

libunwind/src/UnwindRegistersSave.S

@@ -1235,19 +1235,19 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
 
 #elif defined(__riscv)
 
-.macro save_fpr num
+.macro save_fpr num, ctxreg
 #ifdef __CHERI_PURE_CAPABILITY__
-  cfsd   f\num, (__SIZEOF_CHERI_CAPABILITY__ * 32 + 8 * \num)(ca0)
+  cfsd   f\num, (__SIZEOF_CHERI_CAPABILITY__ * 32 + 8 * \num)(c\ctxreg)
 #else
-  FSTORE f\num, (8 * 32 + 8 * \num)(a0)
+  FSTORE f\num, (8 * 32 + 8 * \num)(\ctxreg)
 #endif
 .endm
 
-.macro save_gpr num
+.macro save_gpr num, ctxreg
 #ifdef __CHERI_PURE_CAPABILITY__
-  csc   c\num, (__SIZEOF_CHERI_CAPABILITY__ * \num)(ca0)
+  csc   c\num, (__SIZEOF_CHERI_CAPABILITY__ * \num)(c\ctxreg)
 #else
-  ISTORE x\num, (8 * \num)(a0)
+  ISTORE x\num, (8 * \num)(\ctxreg)
 #endif
 .endm
 
@@ -1264,12 +1264,12 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
   ISTORE    x1, (8 * 0)(a0) // store ra as pc
 #endif
   .irp i,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
-    save_gpr x\i, (RISCV_ISIZE * \i)(a0)
+    save_gpr \i, a0
   .endr
 
 # if defined(__riscv_flen)
   .irp i,FROM_0_TO_31
-    save_fpr f\i, (RISCV_FOFFSET + RISCV_FSIZE * \i)(a0)
+    save_fpr \i, a0
   .endr
 # endif
 

libunwind/src/assembly.h

@@ -35,8 +35,12 @@
 #elif defined(__APPLE__) && defined(__aarch64__)
 #define SEPARATOR %%
 #elif defined(__riscv)
+#ifdef __CHERI_PURE_CAPABILITY__
+# define RISCV_FOFFSET (__SIZEOF_CHERI_CAPABILITY__ * 32)
+#else
 # define RISCV_ISIZE (__riscv_xlen / 8)
 # define RISCV_FOFFSET (RISCV_ISIZE * 32)
+#endif
 # if defined(__riscv_flen)
 #  define RISCV_FSIZE (__riscv_flen / 8)
 # endif

libunwind/test/CMakeLists.txt

@@ -44,15 +44,15 @@ set(_LIBUNWIND_TEST_BINARIES)
 option(LIBUINWIND_BUILD_STATIC_TEST_BINARIES "build static test binaries" ON)
 foreach(_test_path ${_LIBUNWIND_TESTS})
   get_filename_component(_test "${_test_path}" NAME_WE)
-  if ("${_test}" MATCHES ".*bad_unwind_info.*")
+  if ("${_test}" MATCHES ".*bad_unwind_info.*" OR "${_test}" MATCHES ".*scalable_vectors.*")
     continue()  # Only works for a subset of architectures
   endif()
   string(REGEX MATCH ".*exceptions.*" _has_exceptions ${_test})
   if (_has_exceptions)
-    set(_common_libs ${_cxx_abi_link_flag} -lpthread -lc -lpthread -ldl)
+    set(_common_libs unwind-headers ${_cxx_abi_link_flag} -lpthread -lc -lpthread -ldl)
     set(_common_flags -fexceptions)
   else()
-    set(_common_libs -lpthread -lc -lpthread -ldl)
+    set(_common_libs unwind-headers -lpthread -lc -lpthread -ldl)
     set(_common_flags -fno-exceptions)
   endif()
   foreach(_opt "" -O0 -O1 -O2 -O3)