Skip to content

Commit

Permalink
fixed the issues which are raised in issue tracker
Browse files Browse the repository at this point in the history
  • Loading branch information
@sadhanareddy
sadhanareddy committed Jul 15, 2016
1 parent decffec commit 67a6cf1
Show file tree
Hide file tree
Showing 89 changed files with 732 additions and 850 deletions.
23 changes: 13 additions & 10 deletions src/lab/List of experiments.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,6 +78,9 @@
background-color: #e59400;
border: solid 1px black;
}
.desc{
cursor: pointer;
}
</style>

<script type="text/javascript">
Expand Down Expand Up @@ -205,62 +208,62 @@ <h1 class="text-h2-lightblue">Very Large Scale Integration Lab</h1><div>
<!-- <a target="_blank" href="final-build/Experiment.php?code=C001">Schematic Design Of Transistor Level Inverter.</a><br> -->
<a href="final-build/EXP_1sep2010/exp1/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Schematic Design Of Transistor Level Inverter</a>
</li><br/>
<p onclick = "panel1();" >see Description</p>
<p class ="desc" onclick = "panel1();" >see Description</p>
<div id="panel1" class ="panel">In this experiment we will learn the basic design of an inverter. Inverter is the most basic component which we can make out using one NMOS and one PMOS transistor. Here you will learn about the basics how inverter works internally, how the transistor are placed inside inverter and how we get the inverted output corresponding to the inputs we provide. We will learn the layout designing and effects of capacitance and effects of width and length of transistor on the output of an inverter.</div>

<li>
<a href="final-build/EXP_1sep2010/exp2/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Schematic Design Of Transistor Level NAND &amp; NOR Gate.</a>
</li><br/>
<p onclick = "panel2();" >see Description</p>
<p class ="desc" onclick = "panel2();" >see Description</p>
<div id="panel2" class ="panel"> In this experiment, we will learn about the series and parallel combination of n-switches and p-switches. Then we will proceed to the transistor level designing of NAND and NOR gate using NMOS and PMOS and also layout designing of the same.
</div>

<li>
<a href="final-build/EXP_1sep2010/exp3/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Schematic Design Of Transistor Level XOR &amp; XNOR Gate.</a>
</li><br/>
<p onclick = "panel3();" >see Description</p>
<p class ="desc" onclick = "panel3();" >see Description</p>
<div id="panel3" class ="panel">In this experiment, we will first learn how to deduce parallel and series combination of n and p-switches given a combinational logic and hence design them, specifically XOR and XNOR. </div>

<li>
<a href="final-build/EXP_1sep2010/exp4/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Schematic Design Of Pass Transistor Logic &amp; Multiplexer.</a> <br>
</li><br/>
<p onclick = "panel4();" >see Description</p>
<p class ="desc" onclick = "panel4();" >see Description</p>
<div id="panel4" class ="panel"> Transmission gates are used in digital circuits to pass or block particular signal from the components. In transmission gates, NMOS and PMOS are parallel connected to each other. Schematic representation of transmission gate and its circuit symbol are shown below. </div>

<li>
<a href="final-build/EXP_1sep2010/exp5/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Delay Estimation In Chain Of Inverters.</a>
</li><br/>
<p onclick = "panel5();" >see Description</p>
<p class ="desc" onclick = "panel5();" >see Description</p>
<div id="panel5" class ="panel">The method of logical effort is one of the methods used to estimate delay in a CMOS circuit. The model describes delay caused by the capacitive load that the logic gate drives and by the topology of the logic gate. As the gate increases delay also increases, but delay depends on the logic function of the gate also. </div>

<li>
<a href="final-build/EXP_1sep2010/exp6/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Schematic Design Of D-Latch and D-Flip Flop.</a>
</li><br/>
<p onclick = "panel6();" >see Description</p>
<p class ="desc" onclick = "panel6();" >see Description</p>
<div id="panel6" class ="panel"> Latch is an electronic device that can be used to store one bit of information. The D latch is used to capture, or latch the logic level which is present on the Data line when the clock input is high. If the data on the D line changes state while the clock pulse is high, then the output, Q, follows the input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch. </div>

<li>
<a href="final-build/EXP_1sep2010/exp7/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Spice Code Platform.</a>
</li><br/>
<p onclick = "panel7();" >see Description</p>
<p class ="desc" onclick = "panel7();" >see Description</p>
<div id="panel7" class ="panel"> In the experiments we have done till now we have designed gates by arranging transistors in various fashions .The simulation of these designs gave graphs of output voltages and we analyzed how these graph changes with varying different parameters of the transistor. Now when you place a transistor on screen there is a back end code which tells a simulator what are the points to which the transistor's substrate,gate,drain,source are connected. The language in which this information is conveyed is spice. </div>

<li>
<a href="final-build/EXP_1sep2010/exp8/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Design Of D-Flip Flop Using Verilog.</a>
</li><br/>
<p onclick = "panel8();" >see Description</p>
<p class ="desc" onclick = "panel8();" >see Description</p>
<div id="panel8" class ="panel"> Till now we have dealt with transistor level issues involved in designing a gate and studied the effects on the waveforms on changing various parameters of transistor(length and width) .The graphs we have seen till now will gives the corresponding analog output voltages. In the earlier experiments, when a transistor was placed and connections were made a spice code was written in the back end. We learned spice in the previous experiment . Now we proceed towards digital level designing of circuits for example lets take an or gate in the second experiment was we arranged pmos and nmos in a particular fashion and simulated to obtain a graph , changing the parameters we analyzed how the rise time ,fall time ,delay etc. changes. If you observe the graph you will find that the input changes from low value near 0 V to high value near 5V ,the rise is not steep one but gradual . In digital designing we will bother only about two levels 0 and 1(a threshold is determined i.e. voltages below threshold will be 0 and those above will be 1 )As we move towards digital designing we shift our concerns from how does the analog voltage changes to how to generate a desired output from a given sequence of inputs. For instance now we will visualize gate as an entity which will gives the desired truth table. </div>

<li>
<a href="final-build/EXP_1sep2010/exp9/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Design Of Digital Circuits Using Verilog.</a>
</li><br/>
<p onclick = "panel9();" >see Description</p>
<p class ="desc" onclick = "panel9();" >see Description</p>
<div id="panel9" class ="panel"> Verilog is language commonly used in designing digital systems. It is a hardware description language, which means that it is substantially different from any other language you might have encountered so far. Even though it does have control flow statements and variables, it relies primarily on logic functions.It is a textual format for describing electronic circuits and systems. </div>

<li>
<a href="final-build/EXP_1sep2010/layout/Introduction.html?domain=Computer Science & Engineering&lab=Welcome to VLSI lab!">Layout Design.</a>
</li><br/>
<p onclick = "panel10();" >see Description</p>
<p class ="desc" onclick = "panel10();" >see Description</p>
<div id="panel10" class ="panel"> Under Construction. </div>

</ul>
Expand Down
4 changes: 2 additions & 2 deletions src/lab/final-build/EXP_1sep2010/exp1/Objective.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,8 +101,8 @@ <h2 class="text-h2-lightblue" style=" margin-bottom: 20px; margin-top: 10px; "><
<h1 class="text-h2-lightblue">Schematic Design Of Transistor Level Inverter.</h1><div class="content" id="lab-article-section-2-content">
<!-- <font size="3"> -->
<p>(a) To design transistor level schematic of an Inverter using<br><br> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<b>*</b> Complementary CMOS logic<br> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<b>*</b> Pseudo NMOS logic<br> </p><br>
<p>(b)To find the effect of load capacitance on the rise time and fall time and hence delay of output waveform.</p><br>
<p>(c)To find the effect of W/L of transistors on the output waveform.</p><br>
<p>(b) To find the effect of load capacitance on the rise time and fall time and hence delay of output waveform.</p><br>
<p>(c) To find the effect of W/L of transistors on the output waveform.</p><br>
<!-- </font> -->

</div> </div>
Expand Down
2 changes: 1 addition & 1 deletion src/lab/final-build/EXP_1sep2010/exp1/Quiz.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -194,7 +194,7 @@ <h1 class="text-h2-lightblue">Schematic Design Of Transistor Level Inverter</h1>
</ol>

<input type="button" onClick="checkQuiz()" value="check quiz">
<input type="button" value="Reset" onClick="document.quiz.reset()">
<input type="button" value="Reset" onClick="window.location.reload();document.quiz.reset();">
<hr>
<textarea cols="80" rows="10" name="output"></textarea>
</form>
Expand Down
2 changes: 1 addition & 1 deletion src/lab/final-build/EXP_1sep2010/exp1/References.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ <h1 class="text-h2-lightblue">Schematic Design Of Transistor Level Inverter</h1>
<font size="3">
<ol>
<li><b>"Principles of cmos vlsi design"</b>by Weste-Eshraghian</li><br>
<li> http://www.iue.tuwien.ac.at/phd/pichler/node75.html http://www.hitequest.com/Kiss/VLSI.html</li><br>
<!-- <li> http://www.iue.tuwien.ac.at/phd/pichler/node75.html http://www.hitequest.com/Kiss/VLSI.html</li><br> -->
<li><b>CMOS: Circuit Design, Layout, and Simulation, Third Edition</b> by Bacor, R. Jacob. Wiley-IEEE. pp. 1174.Chen, Wai-Kai (ed) (2006). </li><br>
<li><b>The VLSI Handbook, Second Edition (Electrical Engineering Handbook)</b> by Boca Raton: CRC. ISBN 0-8493-4199-X.</li><br><li>http://jas.eng.buffalo.edu/education/fab/NMOS/nmos.html</li><br>
<ol>
Expand Down
2 changes: 1 addition & 1 deletion src/lab/final-build/EXP_1sep2010/exp2/Feedback.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -93,7 +93,7 @@ <h2 class="text-h2-lightblue" style=" margin-bottom: 20px; margin-top: 10px; "><
<div class="row">
<div class="col-md-2 sidebar-col-2">
<!--edit1-->
<a href="Introduction.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Introduction</h3></a><a href="Objective.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Objective</h3></a><a href="Theory.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Theory</h3></a><a href="Procedure.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Procedure</h3></a><a href="Simulator.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Simulator</h3></a><a href="Quiz.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Quiz</h3></a><a href="References.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">References</h3></a><a href="Feedback.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Feedback</h3></a> </div>
<a href="Introduction.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Introduction</h3></a><a href="Objective.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Objective</h3></a><a href="Theory.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Theory</h3></a><a href="Procedure.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Procedure</h3></a><a href="Manual.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Manual</h3></a><a href="Simulator.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Simulator</h3></a><a href="Quiz.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Quiz</h3></a><a href="References.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">References</h3></a><a href="Feedback.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Feedback</h3></a> </div>

<div class="col-md-10 lab-list-col-10">

Expand Down
2 changes: 1 addition & 1 deletion src/lab/final-build/EXP_1sep2010/exp2/Introduction.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -93,7 +93,7 @@ <h2 class="text-h2-lightblue" style=" margin-bottom: 20px; margin-top: 10px; "><
<div class="row">
<div class="col-md-2 sidebar-col-2">
<!--edit1-->
<a href="Introduction.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Introduction</h3></a><a href="Objective.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Objective</h3></a><a href="Theory.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Theory</h3></a><a href="Procedure.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Procedure</h3></a><a href="Simulator.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Simulator</h3></a><a href="Quiz.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Quiz</h3></a><a href="References.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">References</h3></a><a href="Feedback.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Feedback</h3></a> </div>
<a href="Introduction.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Introduction</h3></a><a href="Objective.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Objective</h3></a><a href="Theory.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Theory</h3></a><a href="Procedure.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Procedure</h3></a><a href="Manual.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Manual</h3></a><a href="Simulator.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Simulator</h3></a><a href="Quiz.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Quiz</h3></a><a href="References.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">References</h3></a><a href="Feedback.html?domain=Computer Science & Engineering&lab=VLSI LAB" class="sidebar-a" > <h3 class="text-h3-darkblue" style="margin-top: 2px;">Feedback</h3></a> </div>

<div class="col-md-10 lab-list-col-10">

Expand Down
Loading

0 comments on commit 67a6cf1

Please sign in to comment.