| Discipline | Engineering |
|---|---|
| Lab | Digital Electronics |
| Experiment | 2. Construction of half/ full adder using XOR and NAND gates and verification of its operation. |
This experiment is to verify the truth table of half adder and full adder by using XOR and NAND gates respectively and analyse the working of half adder and full adder circuit with the help of LEDs in simulator 1 and verify the truth table only of half adder and full adder in simulator 2.
| Name of Developer | R.S. Anand |
|---|---|
| Institute | IIT Roorkee |
| Email id | anandfee@gmail.com |
| Department | Electrical Engineering |
| SrNo | Name | Faculty or Student | Department | Institute | Email id |
|---|---|---|---|---|---|
| 1 | R.S. Anand | Faculty | Electrical Engineering | IIT Roorkee, Roorkee | anandfee@gmail.com |
| 2 | Jasbir Singh | Research Fellow | Electrical Engineering | IIT Roorkee, Roorkee | jasbirjassy6@gmail.com |
| 3 | Rajeev Kumar | Research Fellow | Electrical Engineering | IIT Roorkee, Roorkee | rajeevkumar.rke@gmail.com |
| 4 | Priyanshi Agarwal | Research Fellow | Electrical Engineering | IIT Roorkee, Roorkee | priyanshi.a07@gmail.com |