Merge pull request #1 from virtual-labs/dev

Dev
virtual-labs · Aug 11, 2021 · d4742f6 · d4742f6
2 parents fa8c2dd + b7b555c
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diff --git a/experiment-descriptor.json b/experiment-descriptor.json
@@ -0,0 +1,39 @@
+{
+  "unit-type": "lu",
+  "label": "",
+  "basedir": ".",
+  "units": [
+    {
+      "unit-type": "aim"
+    },
+    {
+      "target": "theory.html",
+      "source": "theory.md",
+      "label": "Theory",
+      "unit-type": "task",
+      "content-type": "text"
+    },
+    {
+      "target": "procedure.html",
+      "source": "procedure.md",
+      "label": "Procedure",
+      "unit-type": "task",
+      "content-type": "text"
+    },
+    {
+      "target": "simulation.html",
+      "source": "simulation/index.html",
+      "label": "Simulation",
+      "unit-type": "task",
+      "content-type": "simulation"
+    },
+    {
+      "target": "references.html",
+      "source": "references.md",
+      "label": "References",
+      "unit-type": "task",
+      "content-type": "text"
+    }
+  ]
+}
+
diff --git a/experiment/aim.md b/experiment/aim.md
@@ -1 +1,7 @@
-### Aim of the experiment
+There are multiple approaches for CPU design.  
+
+1. Single Cycle  
+2. Mutiple Cycle  
+3. Pipelined  
+
+In this lab we shall understand the Single Cycle CPU design for a subset of instructions from the MIPS ISA.
diff --git a/experiment/experiment-name.md b/experiment/experiment-name.md
@@ -1 +1 @@
-## Experiment name
+### Single Cycle
diff --git a/experiment/objective.md b/experiment/objective.md
@@ -0,0 +1,2 @@
+- The objective of this experiment is to learn the design principles behind a Single Cycle CPU using a subset of MIPS ISA as example.
+
diff --git a/experiment/posttest.js b/experiment/posttest.js
diff --git a/experiment/pretest.js b/experiment/pretest.js
diff --git a/experiment/procedure.md b/experiment/procedure.md
@@ -1 +1,2 @@
-### Procedure
+Procedure is also explained in the experiment.
+
diff --git a/experiment/references.md b/experiment/references.md
@@ -1 +1 @@
-### Link your references in here
+- Patterson, D. A. and Hennessy, J. L.  Computer Organization and Design: the Hardware/Software Interface. 3rd Edition.
diff --git a/experiment/simulation/index.html b/experiment/simulation/index.html
@@ -7,6 +7,15 @@
 <body>
 		<!-- Your code goes here-->
 
+	<p><a href="./v19.swf">Click Here<script type="text/javascript"> 
+AC_AX_RunContent( 'width','100%','height','100%','src','v19.swf','movie','v19.swf' ); //end AC code
+</script><noscript><object height="100%" width="100%">
+<param name="movie" value="v19.swf"></param>
+<embed src="v19.swf"></embed>
+
+</object></noscript> </a> to perform the experiment</p>
+</p>
+
 	<!-- Add JS at the bottom of HTML file --> 
         <script src="./js/main.js"></script>
 </body>

diff --git a/experiment/simulation/v19.html b/experiment/simulation/v19.html
@@ -0,0 +1,33 @@
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+  ga('create', 'UA-42255654-1', 'virtual-labs.ac.in');
+  ga('send', 'pageview');
+
+</script>
+<!-- Google Analytics Code ends here -->
+</head>
+<body><!--Google Tag Manager (noscript)--><noscript class="gtm"><iframe height="0" src="https://www.googletagmanager.com/ns.html?id=GTM-W59SWTR" style="display:none;visibility:hidden" width="0"></iframe></noscript><!--End Google Tag Manager (noscript)-->
+<object classid="clsid:d27cdb6e-ae6d-11cf-96b8-444553540000" codebase="http://download.macromedia.com/pub/shockwave/
+    cabs/flash/swflash.cab#version=6,0,40,0" height="100%" id="intro" width="100%"> 
+
+  <param name="movie" value="v19.swf"></param> 
+
+  <param name="quality" value="high"></param> 
+
+  <embed align="" height="100%" name="v19" pluginspage="http://www.macromedia.com/go/getflashplayer" quality="high" src="v19.swf" type="application/x-shockwave-flash" width="100%"></embed> 
+
+
+</object>
+
+
+</body></html>
diff --git a/experiment/simulation/v19.swf b/experiment/simulation/v19.swf
diff --git a/experiment/theory.md b/experiment/theory.md
@@ -1 +1,4 @@
-### Link your theory in here
+- In Single Cycle CPU design approach each instruction takes exactly one clock cycle to execute.  
+- In Multicycle CPU each instruction multiple clock cycles to execute.  
+- In Pipelined approach instruction execution takes place in a overlapped fashion.  
+- The instructions supported by the Single Cycle cpu in our experiment and how to microcode new instructions are all given as a part of the experiment itself.