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[Core] Asynchronous Output Processor #7049
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👋 Hi! Thank you for contributing to the vLLM project. Once the PR is approved and ready to go, please make sure to run full CI as it is required to merge (or just use auto-merge). To run full CI, you can do one of these:
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@megha95 This is a good progress! Left some comments.
vllm/config.py
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@@ -129,6 +129,7 @@ def __init__( | |||
skip_tokenizer_init: bool = False, | |||
served_model_name: Optional[Union[str, List[str]]] = None, | |||
multimodal_config: Optional["MultiModalConfig"] = None, | |||
use_output_proc_callback: Optional[bool] = False, |
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I think @WoosukKwon proposal to make the async callback default is a good direction, so we can see the benefits already from this PR. You can enable the callback by default and disable it only for the cases where it does not work currently (beam search, etc...). Follow up PRs can add the missing features.
vllm/engine/llm_engine.py
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required if the worker is to perform async forward pass to next step. | ||
""" | ||
for seq_group_metadata, sequence_group_outputs in zip( | ||
seq_group_metadata_list, output): |
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As we discussed, most likely you need to do seq.is_finished() check here before doing append_token(..)
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Updated now. Thanks for pointing this out.
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Did a second pass, left comments
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vllm/config.py
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# TO DO: assert no pipeline parallelism | ||
# TO DO: assert no spec decoding |
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What are the issues in supporting these two features?
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Supporting spec decoding will need more thought. Mostly because, execute_model
inside spec dec's step is quite different from non-spec dec codepath and we need to figure out the right place to call the callback. Pipeline parallelism should be easier, and can be done in follow-up PR.
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Supporting spec decoding will need more thought. Mostly because,
execute_model
inside spec dec's step is quite different from non-spec dec codepath and we need to figure out the right place to call the callback. Pipeline parallelism should be easier, and can be done in follow-up PR.
Hi, we have better performance with Asynchronous Output Processor, do we have any schedule to support async in spec dec's path? thanks
@comaniac would be good to get your quick feedback on this PR |
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vllm/config.py
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self.use_output_proc_callback = False | ||
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if speculative_config: | ||
self.use_output_proc_callback = False |
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Also need a warning?
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added
# For async output processing, we need to swap cache buffers between | ||
# iterations. I.e. since the output processing is lagged one step, | ||
# we cannot reuse the cached objects immediately when the schedule() | ||
# is called again, but only when schedule() is called the second time. |
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Why the second time is guaranteed to be available?
vllm/core/scheduler.py
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scheduler_outputs = self._schedule() | ||
now = time.time() | ||
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if not self.cache_config.enable_prefix_caching: | ||
common_computed_block_nums = [] | ||
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# TODO: Combine multi-step and async postprocessor | ||
allow_output_proc_callback: bool = ( |
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Why not just combining this logic into the _allow_output_proc_callback function?
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It may be possible, will see if I can do it.
vllm/core/scheduler.py
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# Avoid deque alloc | ||
self.tmp_queue: Deque[SequenceGroup] = deque() |
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Can you say more about this? Or use a better name for this queue. It's hard to catch its functionality in the rest of its use cases.
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Its a deque acting as a temporary buffer to store the new seqs in running queue. It's only used inside free_finished_seq_groups
, we save some time by avoiding re-allocation during each step.
# Skip double logging when using async output proc | ||
if finished_before and idx in finished_before: | ||
actual_num_batched_tokens -= 1 | ||
continue |
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I can't connect the comment and the code. Can you elaborate it?
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actual_num_batched_tokens -= 1
is required to avoid double-counting. With async output proc, number of batched tokens is already counted since its lagged by a step. If we have a token that was finished before, we won't count it again. This does not happen with non-async logging.
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@comaniac @WoosukKwon thanks for the detailed reviews, I think we addressed all of the comments, going over the final CI tests with @megha95 and some issue Woosuk found with beam search. |
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@megha95 @alexm-neuralmagic Huge thanks for the PR! Also, thanks a lot for the kind intro and explanation of this PR.
I'm happy with merging this PR once the remaining super-minor issues are fixed and the PR passes the CI again.
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Thanks @megha95 @alexm-neuralmagic for the great work!
Do you have a sense for how much of the speedup comes from removal of the scheduling from the critical path vs removal of detokenization?
@njhill Thank you for the review. To answer your question:
We haven't removed scheduling from critical path. Most of the speedup in this PR comes from removing detokenization, |
@megha95 @alexm-neuralmagic Thanks again for your great work! |
It seems that this PR is causing the LoRA tests to fail on Before this PR on Can those who worked on this PR look into the issue further? |
@youkaichao @DarkLight1337 Having a look. |
Co-authored-by: Alexander Matveev <alexm@neuralmagic.com>
Co-authored-by: Alexander Matveev <alexm@neuralmagic.com>
FILL IN THE PR DESCRIPTION HERE This PR refer to [vllm-project#7049](vllm-project#7049) to implement Asynchronous Output Processor on HPU. It is open by default, to disable it, please pass the `--disable_async_output_proc` flag. From my local test on latest habana_main branch(commit 29fb5ed), the throughput improves from 3847 TPS to 4011 TPS. **BEFORE SUBMITTING, PLEASE READ THE CHECKLIST BELOW AND FILL IN THE DESCRIPTION ABOVE** --- <details> <!-- inside this <details> section, markdown rendering does not work, so we use raw html here. --> <summary><b> PR Checklist (Click to Expand) </b></summary> <p>Thank you for your contribution to vLLM! Before submitting the pull request, please ensure the PR meets the following criteria. This helps vLLM maintain the code quality and improve the efficiency of the review process.</p> <h3>PR Title and Classification</h3> <p>Only specific types of PRs will be reviewed. The PR title is prefixed appropriately to indicate the type of change. Please use one of the following:</p> <ul> <li><code>[Bugfix]</code> for bug fixes.</li> <li><code>[CI/Build]</code> for build or continuous integration improvements.</li> <li><code>[Doc]</code> for documentation fixes and improvements.</li> <li><code>[Model]</code> for adding a new model or improving an existing model. Model name should appear in the title.</li> <li><code>[Frontend]</code> For changes on the vLLM frontend (e.g., OpenAI API server, <code>LLM</code> class, etc.) </li> <li><code>[Kernel]</code> for changes affecting CUDA kernels or other compute kernels.</li> <li><code>[Core]</code> for changes in the core vLLM logic (e.g., <code>LLMEngine</code>, <code>AsyncLLMEngine</code>, <code>Scheduler</code>, etc.)</li> <li><code>[Hardware][Vendor]</code> for hardware-specific changes. Vendor name should appear in the prefix (e.g., <code>[Hardware][AMD]</code>).</li> <li><code>[Misc]</code> for PRs that do not fit the above categories. Please use this sparingly.</li> </ul> <p><strong>Note:</strong> If the PR spans more than one category, please include all relevant prefixes.</p> <h3>Code Quality</h3> <p>The PR need to meet the following code quality standards:</p> <ul> <li>We adhere to <a href="https://google.github.io/styleguide/pyguide.html">Google Python style guide</a> and <a href="https://google.github.io/styleguide/cppguide.html">Google C++ style guide</a>.</li> <li>Pass all linter checks. Please use <a href="https://github.com/vllm-project/vllm/blob/main/format.sh"><code>format.sh</code></a> to format your code.</li> <li>The code need to be well-documented to ensure future contributors can easily understand the code.</li> <li>Include sufficient tests to ensure the project to stay correct and robust. This includes both unit tests and integration tests.</li> <li>Please add documentation to <code>docs/source/</code> if the PR modifies the user-facing behaviors of vLLM. It helps vLLM user understand and utilize the new features or changes.</li> </ul> <h3>Adding or changing kernels</h3> <p>Each custom kernel needs a schema and one or more implementations to be registered with PyTorch.</p> <ul> <li>Make sure custom ops are registered following PyTorch guidelines: <a href="https://pytorch.org/tutorials/advanced/cpp_custom_ops.html#cpp-custom-ops-tutorial">Custom C++ and CUDA Operators</a> and <a href="https://docs.google.com/document/d/1_W62p8WJOQQUzPsJYa7s701JXt0qf2OfLub2sbkHOaU">The Custom Operators Manual</a></li> <li>Custom operations that return <code>Tensors</code> require meta-functions. Meta-functions should be implemented and registered in python so that dynamic dims can be handled automatically. See above documents for a description of meta-functions.</li> <li>Use <a href="https://pytorch.org/docs/stable/library.html#torch.library.opcheck"><code>torch.libary.opcheck()</code></a> to test the function registration and meta-function for any registered ops. See <code>tests/kernels</code> for examples.</li> <li>When changing the C++ signature of an existing op, the schema must be updated to reflect the changes.</li> <li>If a new custom type is needed, see the following document: <a href="https://docs.google.com/document/d/18fBMPuOJ0fY5ZQ6YyrHUppw9FA332CpNtgB6SOIgyuA">Custom Class Support in PT2</a>. </ul> <h3>Notes for Large Changes</h3> <p>Please keep the changes as concise as possible. For major architectural changes (>500 LOC excluding kernel/data/config/test), we would expect a GitHub issue (RFC) discussing the technical design and justification. Otherwise, we will tag it with <code>rfc-required</code> and might not go through the PR.</p> <h3>What to Expect for the Reviews</h3> <p>The goal of the vLLM team is to be a <i>transparent reviewing machine</i>. We would like to make the review process transparent and efficient and make sure no contributor feel confused or frustrated. However, the vLLM team is small, so we need to prioritize some PRs over others. Here is what you can expect from the review process: </p> <ul> <li> After the PR is submitted, the PR will be assigned to a reviewer. Every reviewer will pick up the PRs based on their expertise and availability.</li> <li> After the PR is assigned, the reviewer will provide status update every 2-3 days. If the PR is not reviewed within 7 days, please feel free to ping the reviewer or the vLLM team.</li> <li> After the review, the reviewer will put an <code> action-required</code> label on the PR if there are changes required. The contributor should address the comments and ping the reviewer to re-review the PR.</li> <li> Please respond to all comments within a reasonable time frame. If a comment isn't clear or you disagree with a suggestion, feel free to ask for clarification or discuss the suggestion. </li> </ul> <h3>Thank You</h3> <p> Finally, thank you for taking the time to read these guidelines and for your interest in contributing to vLLM. Your contributions make vLLM a great tool for everyone! </p> </details>
Co-authored-by: Alexander Matveev <alexm@neuralmagic.com> Signed-off-by: Alvant <alvasian@yandex.ru>
Co-authored-by: Alexander Matveev <alexm@neuralmagic.com>
This PR is an implementation for RFC #6913 .
Following changes were made:
_process_model_outputs
andscheduler.schedule()
were updating deque and free-ing memory of finished sequences._advance_to_next_step
inLLMEngine
that does small but necessary steps in critical path: eg: appending new token id and updating prefill sequences' statuses to decode.execute_model
so thatprocess_model_outputs
is triggered right before sampler insideModelRunner
. Since GPU always runs ahead of CPU, this allows for complete overlap with cuda graph forward pass in each decoding stepResults
Throughput improves by 11% for Llama3.1-8B FP8 on 1xH100. Results are even better at high batch sizes. With my own benchmarking setup, I see 1.3x increase in throughput at high RPS.
There's a follow-up PR # that combines async output processor with multi-step and shows promising results. 30% improvement in TPOT.
Without async output processor
With async output processor
To do: