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minor update
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@tinebp
tinebp committed Oct 21, 2024
1 parent fccbadf commit 2b3d1f0
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Showing 3 changed files with 67 additions and 34 deletions.
13 changes: 7 additions & 6 deletions hw/rtl/core/VX_operands.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ module VX_operands import VX_gpu_pkg::*; #(
wire [NUM_BANKS-1:0] gpr_rd_valid, gpr_rd_ready;
wire [NUM_BANKS-1:0] gpr_rd_valid_st1, gpr_rd_valid_st2;
wire [NUM_BANKS-1:0][PER_BANK_ADDRW-1:0] gpr_rd_addr, gpr_rd_addr_st1;
wire [NUM_BANKS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data_st1, gpr_rd_data_st2;
wire [NUM_BANKS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data_st2;
wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_rd_req_idx, gpr_rd_req_idx_st1, gpr_rd_req_idx_st2;

wire pipe_ready_in;
Expand Down Expand Up @@ -178,14 +178,14 @@ module VX_operands import VX_gpu_pkg::*; #(
wire pipe_valid2_st1 = pipe_valid_st1 && ~has_collision_st1;

VX_pipe_buffer #(
.DATAW (NUM_BANKS * (1 + REQ_SEL_WIDTH + REGS_DATAW) + META_DATAW)
.DATAW (NUM_BANKS * (1 + REQ_SEL_WIDTH) + META_DATAW)
) pipe_reg2 (
.clk (clk),
.reset (reset),
.valid_in (pipe_valid2_st1),
.ready_in (pipe_ready_st1),
.data_in ({gpr_rd_valid_st1, gpr_rd_req_idx_st1, gpr_rd_data_st1, pipe_data_st1}),
.data_out ({gpr_rd_valid_st2, gpr_rd_req_idx_st2, gpr_rd_data_st2, pipe_data_st2}),
.data_in ({gpr_rd_valid_st1, gpr_rd_req_idx_st1, pipe_data_st1}),
.data_out ({gpr_rd_valid_st2, gpr_rd_req_idx_st2, pipe_data_st2}),
.valid_out(pipe_valid_st2),
.ready_out(pipe_ready_st2)
);
Expand Down Expand Up @@ -270,7 +270,8 @@ module VX_operands import VX_gpu_pkg::*; #(
`ifdef GPR_RESET
.RESET_RAM (1),
`endif
.OUT_REG (0)
.OUT_REG (1),
.RDW_MODE ("U")
) gpr_ram (
.clk (clk),
.reset (reset),
Expand All @@ -280,7 +281,7 @@ module VX_operands import VX_gpu_pkg::*; #(
.waddr (gpr_wr_addr),
.wdata (writeback_if.data.data),
.raddr (gpr_rd_addr_st1[b]),
.rdata (gpr_rd_data_st1[b])
.rdata (gpr_rd_data_st2[b])
);
end

Expand Down
76 changes: 54 additions & 22 deletions hw/rtl/libs/VX_dp_ram.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ module VX_dp_ram #(
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter LUTRAM = 0,
parameter `STRING RDW_MODE = "R", // R: read-first, W: write-first
parameter `STRING RDW_MODE = "R", // R: read-first, W: write-first, U: undefined
parameter RDW_ASSERT = 0,
parameter RESET_RAM = 0,
parameter INIT_ENABLE = 0,
Expand All @@ -42,7 +42,7 @@ module VX_dp_ram #(
`UNUSED_PARAM (LUTRAM)

`STATIC_ASSERT(!(WRENW * WSELW != DATAW), ("invalid parameter"))
`STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W"), ("invalid parameter"))
`STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W" || RDW_MODE == "U"), ("invalid parameter"))
`UNUSED_PARAM (RDW_ASSERT)

`define RAM_INITIALIZATION \
Expand Down Expand Up @@ -76,70 +76,95 @@ module VX_dp_ram #(
end
`endif
if (OUT_REG) begin : g_sync
wire cs = read || write;
if (FORCE_BRAM) begin : g_bram
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
(* rw_addr_collision = "yes" *) `USE_BLOCK_BRAM `RAM_ARRAY
`UNUSED_VAR (wren)
`RAM_INITIALIZATION
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
addr_reg <= raddr;
end
end
assign rdata = ram[addr_reg];
end else begin : g_old_data
end else if (RDW_MODE == "R") begin : g_read_first
`USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin : g_undefined
`USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE
end
if (read) begin
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end
end else begin : g_auto
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
(* rw_addr_collision = "yes" *) `RAM_ARRAY
`UNUSED_VAR (wren)
`RAM_INITIALIZATION
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
addr_reg <= raddr;
end
end
assign rdata = ram[addr_reg];
end else begin : g_old_data
end else if (RDW_MODE == "R") begin : g_read_first
`RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
`RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE
end
if (read) begin
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end
end
end else begin : g_async
`UNUSED_VAR (read)
if (FORCE_BRAM) begin : g_bram
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
`USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand All @@ -148,7 +173,7 @@ module VX_dp_ram #(
end
end
assign rdata = ram[raddr];
end else begin : g_old_data
end else begin : g_read_first
`NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand All @@ -159,7 +184,7 @@ module VX_dp_ram #(
assign rdata = ram[raddr];
end
end else begin : g_auto
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
`RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand All @@ -168,7 +193,7 @@ module VX_dp_ram #(
end
end
assign rdata = ram[raddr];
end else begin : g_old_data
end else begin : g_read_first
`NO_RW_RAM_CHECK `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand Down Expand Up @@ -200,29 +225,36 @@ module VX_dp_ram #(
end

if (OUT_REG) begin : g_sync
wire cs = read || write;
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
addr_reg <= raddr;
end
end
assign rdata = ram[addr_reg];
end else begin : g_old_data
end else if (RDW_MODE == "R") begin : g_read_first
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (read || write) begin
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin : g_undefined
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read) begin
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end
end else begin : g_async
`UNUSED_VAR (read)
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
assign rdata = ram[raddr];
end else begin : g_old_data
end else begin : g_read_first
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
Expand Down
12 changes: 6 additions & 6 deletions hw/rtl/libs/VX_sp_ram.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -196,7 +196,7 @@ module VX_sp_ram #(
end else begin : g_async
`UNUSED_VAR (read)
if (FORCE_BRAM) begin : g_bram
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
`USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand All @@ -205,7 +205,7 @@ module VX_sp_ram #(
end
end
assign rdata = ram[addr];
end else begin : g_old_data
end else begin : g_read_first
`NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand All @@ -216,7 +216,7 @@ module VX_sp_ram #(
assign rdata = ram[addr];
end
end else begin : g_auto
if (RDW_MODE == "W") begin : g_new_data
if (RDW_MODE == "W") begin : g_write_first
`RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand All @@ -225,7 +225,7 @@ module VX_sp_ram #(
end
end
assign rdata = ram[addr];
end else begin : g_old_data
end else begin : g_read_first
`NO_RW_RAM_CHECK `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
Expand Down Expand Up @@ -284,9 +284,9 @@ module VX_sp_ram #(
end
end else begin : g_async
`UNUSED_VAR (read)
if (RDW_MODE == "W") begin : g_rwcheck
if (RDW_MODE == "W") begin : g_write_first
assign rdata = ram[addr];
end else begin : g_no_rwcheck
end else begin : g_read_first
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
Expand Down

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