minor update

vortexgpgpu · Sep 30, 2024 · 2d00cec · 2d00cec
1 parent a303192
commit 2d00cec
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Showing 3 changed files with 30 additions and 21 deletions.
diff --git a/hw/rtl/libs/VX_mem_scheduler.sv b/hw/rtl/libs/VX_mem_scheduler.sv
@@ -433,7 +433,7 @@ module VX_mem_scheduler #(
         end
     end
 
-    if (RSP_PARTIAL != 0) begin : g_rsp_partial
+    if (RSP_PARTIAL != 0 || CORE_REQS == 1) begin : g_rsp_partial
 
         reg [CORE_QUEUE_SIZE-1:0] rsp_sop_r;
 
@@ -459,16 +459,15 @@ module VX_mem_scheduler #(
 
     end else begin : g_rsp_full
 
-        // use flattened arrays for BRAM synthesis compatibility
         reg [(CORE_BATCHES * CORE_CHANNELS * WORD_WIDTH)-1:0] rsp_store [CORE_QUEUE_SIZE-1:0];
-        reg [(CORE_BATCHES * CORE_CHANNELS)-1:0][WORD_WIDTH-1:0] rsp_store_n;
+        reg [CORE_BATCHES-1:0][CORE_CHANNELS-1:0][WORD_WIDTH-1:0] rsp_store_n;
         reg [CORE_REQS-1:0] rsp_orig_mask [CORE_QUEUE_SIZE-1:0];
 
         always @(*) begin
             rsp_store_n = rsp_store[ibuf_raddr];
             for (integer i = 0; i < CORE_CHANNELS; ++i) begin
                 if ((CORE_CHANNELS == 1) || mem_rsp_mask_s[i]) begin
-                    rsp_store_n[rsp_batch_idx * CORE_CHANNELS + i] = mem_rsp_data_s[i];
+                    rsp_store_n[rsp_batch_idx][i] = mem_rsp_data_s[i];
                 end
             end
         end
@@ -489,7 +488,7 @@ module VX_mem_scheduler #(
         for (genvar r = 0; r < CORE_REQS; ++r) begin : g_crsp_data
             localparam i = r / CORE_CHANNELS;
             localparam j = r % CORE_CHANNELS;
-            assign crsp_data[r] = rsp_store_n[i * CORE_CHANNELS + j];
+            assign crsp_data[r] = rsp_store_n[i][j];
         end
 
         assign mem_rsp_ready_s = crsp_ready || ~rsp_complete;

diff --git a/hw/syn/xilinx/xrt/Makefile b/hw/syn/xilinx/xrt/Makefile
@@ -178,9 +178,9 @@ $(BIN_DIR)/emconfig.json:
 
 report: $(XCLBIN_CONTAINER)
 ifeq ($(TARGET), hw)
-	cp $(BUILD_DIR)/_x/logs/link/vivado.log $(BUILD_DIR)/bin/vivado.log
-	cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_full_util_routed.rpt $(BUILD_DIR)/bin/synthesis.log
-	cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin/timing.log
+	cp $(BUILD_DIR)/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log $(BUILD_DIR)/bin
+	cp $(BUILD_DIR)/_x/reports/link/syn/ulp_vortex_afu_1_0_synth_1_ulp_vortex_afu_1_0_utilization_synth.rpt $(BUILD_DIR)/bin
+	cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin
 endif
 
 chipscope:

diff --git a/sim/rtlsim/processor.cpp b/sim/rtlsim/processor.cpp
@@ -152,6 +152,7 @@ class Processor::Impl {
 
     // start
     device_->reset = 0;
+    device_->mem_req_ready = 1;
 
     // wait on device to go busy
     while (!device_->busy) {
@@ -175,6 +176,7 @@ class Processor::Impl {
     device_->dcr_wr_data  = value;
     this->tick();
     device_->dcr_wr_valid = 0;
+    this->tick();
   }
 
 private:
@@ -184,7 +186,6 @@ class Processor::Impl {
     this->dcr_bus_reset();
 
     print_bufs_.clear();
-
     pending_mem_reqs_.clear();
 
     {
@@ -200,12 +201,21 @@ class Processor::Impl {
       device_->clk = 1;
       this->eval();
     }
-
-    device_->mem_req_ready = 1;
   }
 
   void tick() {
-    this->mem_bus_eval();
+
+    device_->clk = 0;
+    this->eval();
+
+    this->mem_bus_eval(0);
+
+    device_->clk = 1;
+    this->eval();
+
+    this->mem_bus_eval(1);
+
+    dram_sim_.tick();
 
     if (!dram_queue_.empty()) {
       auto mem_req = dram_queue_.front();
@@ -221,13 +231,6 @@ class Processor::Impl {
       }
     }
 
-    dram_sim_.tick();
-
-    device_->clk = 0;
-    this->eval();
-    device_->clk = 1;
-    this->eval();
-
   #ifndef NDEBUG
     fflush(stdout);
   #endif
@@ -250,9 +253,14 @@ class Processor::Impl {
     device_->mem_rsp_valid = 0;
   }
 
-  void mem_bus_eval() {
+  void mem_bus_eval(bool clk) {
+    if (!clk) {
+      mem_rd_rsp_ready_ = device_->mem_rsp_ready;
+      return;
+    }
+
     // process memory read responses
-    if (device_->mem_rsp_valid && device_->mem_rsp_ready) {
+    if (device_->mem_rsp_valid && mem_rd_rsp_ready_) {
       device_->mem_rsp_valid = 0;
     }
     if (!device_->mem_rsp_valid) {
@@ -375,6 +383,8 @@ class Processor::Impl {
   VerilatedVcdC *tfp_;
 #endif
 
+  bool mem_rd_rsp_ready_;
+
   RAM* ram_;
 };