minor update

hw/unittest/cache/cachesim.cpp

@@ -47,27 +47,27 @@ void sim_trace_enable(bool enable) {
 }
 
 CacheSim::CacheSim() {
+  // force random values for uninitialized signals
+  Verilated::randReset(2);
+
   // create RTL module instance
   cache_ = new VVX_cache_top();
 
 #ifdef VCD_OUTPUT
   Verilated::traceEverOn(true);
-  trace_ = new VerilatedVcdC;
-  cache_->trace(trace_, 99);
-  trace_->open("trace.vcd");
+  tfp_ = new VerilatedVcdC;
+  cache_->trace(tfp_, 99);
+  tfp_->open("trace.vcd");
 #endif
 
-  // force random values for uninitialized signals
-  Verilated::randReset(2);
-
   ram_ = nullptr;
   mem_rsp_active_ = false;
   snp_req_active_ = false;
 }
 
 CacheSim::~CacheSim() {
 #ifdef VCD_OUTPUT
-  trace_->close();
+  tfp_->close();
 #endif
   delete cache_;
   //need to delete the req and rsp vectors
@@ -112,7 +112,7 @@ void CacheSim::step() {
 void CacheSim::eval() {
   cache_->eval();
 #ifdef VCD_OUTPUT
-  trace_->dump(timestamp);
+  tfp_->dump(timestamp);
 #endif
   ++timestamp;
 }

hw/unittest/cache/cachesim.h

@@ -96,9 +96,9 @@ class CacheSim {
   uint32_t snp_req_size_;
   uint32_t pending_snp_reqs_;
 
-  VVX_cache_top *cache_;
-  RAM *ram_;
+  VVX_cache_top* cache_;
+  RAM* ram_;
 #ifdef VCD_OUTPUT
-  VerilatedVcdC *trace_;
+  VerilatedVcdC* tfp_;
 #endif
 };

hw/unittest/mem_streamer/memsim.cpp

@@ -61,31 +61,31 @@ int generate_rand_mask (int mask) {
 }
 
 MemSim::MemSim() {
+  // force random values for uninitialized signals
+  Verilated::randReset(2);
+
 	// create RTL module instance
 	msu_ = new VVX_mem_scheduler();
 
 #ifdef VCD_OUTPUT
   	Verilated::traceEverOn(true);
-  	trace_ = new VerilatedVcdC;
-  	cache_->trace(trace_, 99);
+  	tfp_ = new VerilatedVcdC;
+  	cache_->trace(tfp_, 99);
   	race_->open("trace.vcd");
 #endif
-
-  // force random values for uninitialized signals
-  Verilated::randReset(2);
 }
 
 MemSim::~MemSim() {
 #ifdef VCD_OUTPUT
-	trace_->close();
+	tfp_->close();
 #endif
 	delete msu_;
 }
 
 void MemSim::eval() {
 	msu_->eval();
 #ifdef VCD_OUTPUT
-	trace_->dump(timestamp++);
+	tfp_->dump(timestamp++);
 #endif
 }
 

hw/unittest/mem_streamer/memsim.h

@@ -1,10 +1,10 @@
 // Copyright © 2019-2023
-// 
+//
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 // http://www.apache.org/licenses/LICENSE-2.0
-// 
+//
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -16,10 +16,8 @@
 #include <iostream>
 #include <unordered_map>
 #include <vector>
-#include <verilated.h>
 #include <verilated_vcd_c.h>
 #include "VVX_mem_scheduler.h"
-#include "VVX_mem_scheduler__Syms.h"
 #include "ram.h"
 
 #define SIM_TIME 5000
@@ -37,7 +35,7 @@ class MemSim {
 private:
     VVX_mem_scheduler *msu_;
 #ifdef VCD_OUTPUT
-    VerilatedVcdC *trace_;
+    VerilatedVcdC* tfp_;
 #endif
 
     void eval();

sim/opaesim/opae_sim.cpp

@@ -13,9 +13,7 @@
 
 #include "opae_sim.h"
 
-#include <verilated.h>
 #include "Vvortex_afu_shim.h"
-#include "Vvortex_afu_shim__Syms.h"
 
 #ifdef VCD_OUTPUT
 #include <verilated_vcd_c.h>
@@ -109,7 +107,7 @@ class opae_sim::Impl {
   , stop_(false)
   , host_buffer_ids_(0)
 #ifdef VCD_OUTPUT
-  , trace_(nullptr)
+  , tfp_(nullptr)
 #endif
   {}
 
@@ -122,9 +120,9 @@ class opae_sim::Impl {
       aligned_free(buffer.second.data);
     }
   #ifdef VCD_OUTPUT
-    if (trace_) {
-      trace_->close();
-      delete trace_;
+    if (tfp_) {
+      tfp_->close();
+      delete tfp_;
     }
   #endif
     if (device_) {
@@ -136,23 +134,23 @@ class opae_sim::Impl {
   }
 
   int init() {
-    // create RTL module instance
-    device_ = new Vvortex_afu_shim();
-
-  #ifdef VCD_OUTPUT
-    Verilated::traceEverOn(true);
-    trace_ = new VerilatedVcdC();
-    device_->trace(trace_, 99);
-    trace_->open("trace.vcd");
-  #endif
-
     // force random values for unitialized signals
     Verilated::randReset(VERILATOR_RESET_VALUE);
     Verilated::randSeed(50);
 
     // turn off assertion before reset
     Verilated::assertOn(false);
 
+    // create RTL module instance
+    device_ = new Vvortex_afu_shim();
+
+  #ifdef VCD_OUTPUT
+    Verilated::traceEverOn(true);
+    tfp_ = new VerilatedVcdC();
+    device_->trace(tfp_, 99);
+    tfp_->open("trace.vcd");
+  #endif
+
     ram_ = new RAM(0, RAM_PAGE_SIZE);
 
   #ifndef NDEBUG
@@ -318,7 +316,7 @@ class opae_sim::Impl {
     device_->eval();
   #ifdef VCD_OUTPUT
     if (sim_trace_enabled()) {
-      trace_->dump(timestamp);
+      tfp_->dump(timestamp);
     }
   #endif
     ++timestamp;
@@ -542,7 +540,7 @@ class opae_sim::Impl {
   std::queue<mem_req_t*> dram_queue_;
 
 #ifdef VCD_OUTPUT
-  VerilatedVcdC *trace_;
+  VerilatedVcdC *tfp_;
 #endif
 };
 

sim/rtlsim/processor.cpp

@@ -13,15 +13,11 @@
 
 #include "processor.h"
 
-#include <verilated.h>
-
 #ifdef AXI_BUS
 #include "VVortex_axi.h"
-#include "VVortex_axi__Syms.h"
 typedef VVortex_axi Device;
 #else
 #include "VVortex.h"
-#include "VVortex__Syms.h"
 typedef VVortex Device;
 #endif
 
@@ -109,23 +105,23 @@ void sim_trace_enable(bool enable) {
 class Processor::Impl {
 public:
   Impl() : dram_sim_(MEM_CLOCK_RATIO) {
-    // create RTL module instance
-    device_ = new Device();
-
-  #ifdef VCD_OUTPUT
-    Verilated::traceEverOn(true);
-    trace_ = new VerilatedVcdC();
-    device_->trace(trace_, 99);
-    trace_->open("trace.vcd");
-  #endif
-
     // force random values for unitialized signals
     Verilated::randReset(VERILATOR_RESET_VALUE);
     Verilated::randSeed(50);
 
     // turn off assertion before reset
     Verilated::assertOn(false);
 
+    // create RTL module instance
+    device_ = new Device();
+
+  #ifdef VCD_OUTPUT
+    Verilated::traceEverOn(true);
+    tfp_ = new VerilatedVcdC();
+    device_->trace(tfp_, 99);
+    tfp_->open("trace.vcd");
+  #endif
+
     ram_ = nullptr;
 
   #ifndef NDEBUG
@@ -151,8 +147,8 @@ class Processor::Impl {
     this->cout_flush();
 
   #ifdef VCD_OUTPUT
-    trace_->close();
-    delete trace_;
+    tfp_->close();
+    delete tfp_;
   #endif
 
     delete device_;
@@ -276,7 +272,7 @@ class Processor::Impl {
     device_->eval();
   #ifdef VCD_OUTPUT
     if (sim_trace_enabled()) {
-      trace_->dump(timestamp);
+      tfp_->dump(timestamp);
     } else {
       exit(-1);
     }
@@ -576,28 +572,28 @@ class Processor::Impl {
     bool ready;
   } mem_req_t;
 
+  std::unordered_map<int, std::stringstream> print_bufs_;
+
+  std::list<mem_req_t*> pending_mem_reqs_;
+
+  std::queue<mem_req_t*> dram_queue_;
+
+  DramSim dram_sim_;
+
   Device* device_;
 
 #ifdef VCD_OUTPUT
-  VerilatedVcdC *trace_;
+  VerilatedVcdC *tfp_;
 #endif
 
-  std::unordered_map<int, std::stringstream> print_bufs_;
-
-  std::list<mem_req_t*> pending_mem_reqs_;
+  RAM* ram_;
 
   bool mem_rd_rsp_active_;
   bool mem_rd_rsp_ready_;
 
   bool mem_wr_rsp_active_;
   bool mem_wr_rsp_ready_;
 
-  RAM *ram_;
-
-  DramSim dram_sim_;
-
-  std::queue<mem_req_t*> dram_queue_;
-
   bool running_;
 };