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cache repl reset
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@tinebp
tinebp committed Jan 21, 2025
1 parent d1f37fc commit fb4527f
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Showing 8 changed files with 46 additions and 48 deletions.
2 changes: 1 addition & 1 deletion hw/rtl/cache/VX_cache.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ module VX_cache import VX_gpu_pkg::*; #(
parameter DIRTY_BYTES = 0,

// Replacement policy
parameter REPL_POLICY = `CS_REPL_CYCLIC,
parameter REPL_POLICY = `CS_REPL_FIFO,

// Request debug identifier
parameter UUID_WIDTH = 0,
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11 changes: 6 additions & 5 deletions hw/rtl/cache/VX_cache_bank.sv
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Expand Up @@ -48,7 +48,7 @@ module VX_cache_bank #(
parameter DIRTY_BYTES = 0,

// Replacement policy
parameter REPL_POLICY = `CS_REPL_CYCLIC,
parameter REPL_POLICY = `CS_REPL_FIFO,

// Request debug identifier
parameter UUID_WIDTH = 0,
Expand Down Expand Up @@ -353,9 +353,11 @@ module VX_cache_bank #(
.clk (clk),
.reset (reset),
.stall (pipe_stall),
.hit_valid (do_lookup_st1 && is_hit_st1 && ~pipe_stall),
.hit_line (line_idx_st1),
.hit_way (way_idx_st1),
.init (do_init_st0),
.lookup_valid(do_lookup_st1 && ~pipe_stall),
.lookup_hit (is_hit_st1),
.lookup_line(line_idx_st1),
.lookup_way (way_idx_st1),
.repl_valid (do_fill_st0 && ~pipe_stall),
.repl_line (line_idx_st0),
.repl_way (victim_way_st0)
Expand Down Expand Up @@ -443,7 +445,6 @@ module VX_cache_bank #(
) cache_data (
.clk (clk),
.reset (reset),
.stall (pipe_stall),
// inputs
.init (do_init_st0),
.fill (do_fill_st0 && ~pipe_stall),
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2 changes: 1 addition & 1 deletion hw/rtl/cache/VX_cache_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
parameter DIRTY_BYTES = 0,

// Replacement policy
parameter REPL_POLICY = `CS_REPL_CYCLIC,
parameter REPL_POLICY = `CS_REPL_FIFO,

// Request debug identifier
parameter UUID_WIDTH = 0,
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2 changes: 0 additions & 2 deletions hw/rtl/cache/VX_cache_data.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,6 @@ module VX_cache_data #(
) (
input wire clk,
input wire reset,
input wire stall,
// inputs
input wire init,
input wire fill,
Expand All @@ -53,7 +52,6 @@ module VX_cache_data #(
output wire [LINE_SIZE-1:0] evict_byteen
);
`UNUSED_PARAM (WORD_SIZE)
`UNUSED_VAR (stall)

wire [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] write_mask;
for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin : g_write_mask
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2 changes: 1 addition & 1 deletion hw/rtl/cache/VX_cache_define.vh
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Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@
///////////////////////////////////////////////////////////////////////////////

`define CS_REPL_RANDOM 0
`define CS_REPL_CYCLIC 1
`define CS_REPL_FIFO 1
`define CS_REPL_PLRU 2

`endif // VX_CACHE_DEFINE_VH
72 changes: 36 additions & 36 deletions hw/rtl/cache/VX_cache_repl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -90,19 +90,23 @@ module VX_cache_repl #(
// Number of associative ways
parameter NUM_WAYS = 1,
// replacement policy
parameter REPL_POLICY = `CS_REPL_CYCLIC
parameter REPL_POLICY = `CS_REPL_FIFO
) (
input wire clk,
input wire reset,
input wire stall,
input wire hit_valid,
input wire [`CS_LINE_SEL_BITS-1:0] hit_line,
input wire [`CS_WAY_SEL_WIDTH-1:0] hit_way,
input wire init,
input wire lookup_valid,
input wire lookup_hit,
input wire [`CS_LINE_SEL_BITS-1:0] lookup_line,
input wire [`CS_WAY_SEL_WIDTH-1:0] lookup_way,
input wire repl_valid,
input wire [`CS_LINE_SEL_BITS-1:0] repl_line,
output wire [`CS_WAY_SEL_WIDTH-1:0] repl_way
);
localparam WAY_SEL_WIDTH = `CS_WAY_SEL_WIDTH;
`UNUSED_VAR (reset)
`UNUSED_VAR (init)
`UNUSED_VAR (stall)

if (NUM_WAYS > 1) begin : g_enable
Expand All @@ -119,26 +123,23 @@ module VX_cache_repl #(
.SIZE (`CS_LINES_PER_BANK),
.WRENW (LRU_WIDTH),
.RDW_MODE ("R"),
`ifdef SIMULATION
.RESET_RAM (1),
`endif
.RADDR_REG (1)
) plru_store (
.clk (clk),
.reset (reset),
.reset (1'b0),
.read (repl_valid),
.write (hit_valid),
.wren (plru_wmask),
.waddr (hit_line),
.write (init || (lookup_valid && lookup_hit)),
.wren (init ? '1 : plru_wmask),
.waddr (lookup_line),
.raddr (repl_line),
.wdata (plru_wdata),
.wdata (init ? '0 : plru_wdata),
.rdata (plru_rdata)
);

plru_decoder #(
.NUM_WAYS (NUM_WAYS)
) plru_dec (
.way_idx (hit_way),
.way_idx (lookup_way),
.lru_data (plru_wdata),
.lru_mask (plru_wmask)
);
Expand All @@ -150,40 +151,39 @@ module VX_cache_repl #(
.way_idx (repl_way)
);

end else if (REPL_POLICY == `CS_REPL_CYCLIC) begin : g_cyclic
// Cyclic replacement policy
`UNUSED_VAR (hit_valid)
`UNUSED_VAR (hit_line)
`UNUSED_VAR (hit_way)
end else if (REPL_POLICY == `CS_REPL_FIFO) begin : g_fifo
// Fifo replacement policy
`UNUSED_VAR (lookup_valid)
`UNUSED_VAR (lookup_hit)
`UNUSED_VAR (lookup_line)
`UNUSED_VAR (lookup_way)

wire [WAY_SEL_WIDTH-1:0] ctr_rdata;
wire [WAY_SEL_WIDTH-1:0] ctr_wdata = ctr_rdata + 1;
wire [WAY_SEL_WIDTH-1:0] fifo_rdata;
wire [WAY_SEL_WIDTH-1:0] fifo_wdata = fifo_rdata + 1;

VX_sp_ram #(
.DATAW (WAY_SEL_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.RDW_MODE ("R"),
`ifdef SIMULATION
.RESET_RAM (1),
`endif
.RADDR_REG (1)
) ctr_store (
) fifo_store (
.clk (clk),
.reset (reset),
.reset (1'b0),
.read (repl_valid),
.write (repl_valid),
.write (init || repl_valid),
.wren (1'b1),
.addr (repl_line),
.wdata (ctr_wdata),
.rdata (ctr_rdata)
.wdata (init ? '0 : fifo_wdata),
.rdata (fifo_rdata)
);

assign repl_way = ctr_rdata;
assign repl_way = fifo_rdata;
end else begin : g_random
// Random replacement policy
`UNUSED_VAR (hit_valid)
`UNUSED_VAR (hit_line)
`UNUSED_VAR (hit_way)
`UNUSED_VAR (lookup_valid)
`UNUSED_VAR (lookup_hit)
`UNUSED_VAR (lookup_line)
`UNUSED_VAR (lookup_way)
`UNUSED_VAR (repl_valid)
`UNUSED_VAR (repl_line)
reg [WAY_SEL_WIDTH-1:0] victim_idx;
Expand All @@ -198,10 +198,10 @@ module VX_cache_repl #(
end
end else begin : g_disable
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (hit_valid)
`UNUSED_VAR (hit_line)
`UNUSED_VAR (hit_way)
`UNUSED_VAR (lookup_valid)
`UNUSED_VAR (lookup_hit)
`UNUSED_VAR (lookup_line)
`UNUSED_VAR (lookup_way)
`UNUSED_VAR (repl_valid)
`UNUSED_VAR (repl_line)
assign repl_way = 1'b0;
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2 changes: 1 addition & 1 deletion hw/rtl/cache/VX_cache_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
parameter DIRTY_BYTES = 0,

// Replacement policy
parameter REPL_POLICY = `CS_REPL_CYCLIC,
parameter REPL_POLICY = `CS_REPL_FIFO,

// Request debug identifier
parameter UUID_WIDTH = 0,
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1 change: 0 additions & 1 deletion hw/syn/xilinx/dut/project.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -138,7 +138,6 @@ proc run_report {} {
# Generate the synthesis report
report_place_status -file place.rpt
report_route_status -file route.rpt
report_timing_summary -file timing.rpt

# Generate timing report
report_timing -nworst 100 -delay_type max -sort_by group -file timing.rpt
Expand Down

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