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.vivado_hls_log_all.xml
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.vivado_hls_log_all.xml
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<?xml version="1.0" encoding="UTF-8"?>
<vivadoHLSLog:LogRoot xmlns:vivadoHLSLog="www.xilinx.com/vivadoHLSLog">
<errorLogs>
<logs>
<synLog/>
<simLog/>
<mgLog/>
<packageLog/>
<csimLog/>
</logs>
</errorLogs>
<warningLogs>
<logs>
<synLog>
<logs message="WARNING: [RTGEN 206-101] Port 'clahe_top/src_TLAST' has no fanin or fanout and is left dangling.
 Please use C simulation to confirm this function argument can be read from or written to." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:38.494+0900" type="Warning"/>
<logs message="WARNING: [SCHED 204-68] The II Violation in module 'calc_lut_body_stream' (Loop: resdistribute2): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
 between 'store' operation ('tileHist_V_addr_6_write_ln354', clahe_fpga/.settings/clahe.cpp:354) of variable 'add_ln214', clahe_fpga/.settings/clahe.cpp:354 on array 'tileHist.V', clahe_fpga/.settings/clahe.cpp:296 and 'load' operation ('oldval.V', clahe_fpga/.settings/clahe.cpp:356) on array 'tileHist.V', clahe_fpga/.settings/clahe.cpp:296." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:12.366+0900" type="Warning"/>
<logs message="WARNING: [SCHED 204-68] The II Violation in module 'calc_lut_body_stream' (Loop: make_histogram): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
 between 'store' operation ('tileHist_V_addr_2_write_ln320', clahe_fpga/.settings/clahe.cpp:320) of constant 210 on array 'tileHist.V', clahe_fpga/.settings/clahe.cpp:296 and 'load' operation ('tileHist_V_load', clahe_fpga/.settings/clahe.cpp:325) on array 'tileHist.V', clahe_fpga/.settings/clahe.cpp:296." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:12.348+0900" type="Warning"/>
<logs message="WARNING: [ANALYSIS 214-52] Found false 'RAW' intra dependency for variable 'tileHist.V' (clahe_fpga/.settings/clahe.cpp:296)." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:10.467+0900" type="Warning"/>
<logs message="WARNING: [XFORM 203-631] Renaming function 'dataflow_in_loop_outer' to 'dataflow_in_loop_out' (clahe_fpga/.settings/clahe.cpp:267:3)" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:09.013+0900" type="Warning"/>
<logs message="WARNING: [XFORM 203-631] Renaming function 'interpolation_stream_2buf' to 'interpolation_stream' (clahe_fpga/.settings/clahe.cpp:15:43)" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:08.704+0900" type="Warning"/>
<logs message="WARNING: [XFORM 203-542] Cannot flatten a loop nest 'body' (clahe_fpga/.settings/clahe.cpp:594:55) in function 'interpolation_stream_2buf' : 


more than one sub loop." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:08.205+0900" type="Warning"/>
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'src.data.V' (clahe_fpga/.settings/clahe.cpp:678)." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:04.732+0900" type="Warning"/>
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'dst.data.V' (clahe_fpga/.settings/clahe.cpp:678)." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:33:04.099+0900" type="Warning"/>
<logs message="WARNING: [HLS 200-471] Dataflow form checks found 1 issue(s) in file clahe_fpga/.settings/clahe.cpp" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:30:03.684+0900" type="Warning"/>
<logs message="WARNING: [HLS 214-111] Streams will behave like static variables inside a dataflow region: clahe_fpga/.settings/clahe.cpp:688:29" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:29:37.402+0900" type="Warning"/>
<logs message="WARNING: [HLS 200-484] The 'config_sdx -optimization_level' command is deprecated and will be removed in a future release." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:29:13.573+0900" type="Warning"/>
<logs message="WARNING: [HLS 200-483] The 'config_sdx -optimization_level' command is deprecated and will be removed in a future release. Use 'config_export -vivado_optimization_level' as its replacement." projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:29:13.562+0900" type="Warning"/>
</synLog>
<simLog>
<logs message="Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL 000 to DSP48E1 instance is invalid.
Time: 1767125 ns Iteration: 11 Process: /apatb_clahe_top_top/AESL_inst_clahe_top/interpolation_stream_U0/clahe_top_fadd_32ns_32ns_32_5_full_dsp_1_U98/clahe_top_ap_fadd_3_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc File: /home/cad/xilinx/Vivado-2019.1/Vivado/2019.1/data/vhdl/src/unisims/primitive/DSP48E1.vhd" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:43:25.842+0900" type="Warning"/>
<logs message="WARNING: [VRFC 10-3499] library name 'floating_point_v7_1_8' of instantiated unit conflicts with visible identifier [/home/hlab/kokihonda/clahe_fpga/solution1/sim/verilog/ip/xil_defaultlib/clahe_top_ap_sitofp_4_no_dsp_32.vhd:196]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package floating_point_v7_1_8.floating_point_v7_1_8_viv_comp
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_8.floating_point_v7_1_8_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_8.floating_point_v7_1_8_exp_table_...
Compiling package mult_gen_v12_0_15.mult_gen_v12_0_15_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_8.floating_point_v7_1_8_pkg
Compiling package floating_point_v7_1_8.flt_utils
Compiling package unisim.vcomponents
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package floating_point_v7_1_8.vt2mutils
Compiling package floating_point_v7_1_8.vt2mcomps
Compiling module xil_defaultlib.clahe_top_AXILiteS_s_axi
Compiling module xil_defaultlib.axis2streams
Compiling module xil_defaultlib.calc_lut_body_stream_mask_table3...
Compiling module xil_defaultlib.calc_lut_body_stream_mask_table3...
Compiling module xil_defaultlib.calc_lut_body_stream_one_half_ta...
Compiling module xil_defaultlib.calc_lut_body_stream_one_half_ta...
Compiling module xil_defaultlib.calc_lut_body_stream_tileHist_V_...
Compiling module xil_defaultlib.calc_lut_body_stream_tileHist_V(...
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=7,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=16,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=24,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=17,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=25,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture rtl of entity floating_point_v7_1_8.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,b_wi...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=48,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture rtl of entity floating_point_v7_1_8.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,b_wi...]
Compiling architecture struct of entity floating_point_v7_1_8.fix_mult_dsp48e1_sgl [\fix_mult_dsp48e1_sgl(registers=...]
Compiling architecture rtl of entity floating_point_v7_1_8.fix_mult [\fix_mult(c_xdevicefamily="zynq"...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=32,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_8.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_8.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [delay_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=2,fast_input=true)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(fast_input=true)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=4,fast_input=true)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=8)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=30,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=18,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture rtl of entity floating_point_v7_1_8.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=30,b_wi...]
Compiling architecture struct of entity floating_point_v7_1_8.flt_round_dsp_opt_full [\flt_round_dsp_opt_full(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_8.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_mult [\flt_mult(c_xdevicefamily="zynq"...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8_viv [\floating_point_v7_1_8_viv(c_xde...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8 [\floating_point_v7_1_8(c_xdevice...]
Compiling architecture clahe_top_ap_fmul_2_max_dsp_32_arch of entity xil_defaultlib.clahe_top_ap_fmul_2_max_dsp_32 [clahe_top_ap_fmul_2_max_dsp_32_d...]
Compiling module xil_defaultlib.clahe_top_fmul_32ns_32ns_32_4_ma...
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=64,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=16,length=0,fast_in...]
Compiling architecture rtl of entity floating_point_v7_1_8.norm_zero_det [\norm_zero_det(data_width=39,nor...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=64)\]
Compiling architecture rtl of entity floating_point_v7_1_8.mux4 [\mux4(c_xdevicefamily="zynq",wid...]
Compiling architecture rtl of entity floating_point_v7_1_8.mux4 [\mux4(c_xdevicefamily="zynq",wid...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=2,length=2)\]
Compiling architecture rtl of entity floating_point_v7_1_8.mux4 [\mux4(c_xdevicefamily="zynq",wid...]
Compiling architecture rtl of entity floating_point_v7_1_8.mux4 [\mux4(c_xdevicefamily="zynq",wid...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=2)\]
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fde_v of entity unisim.FDE [fde_default]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_8.lead_zero_encode [\lead_zero_encode(c_xdevicefamil...]
Compiling architecture rtl of entity floating_point_v7_1_8.shift_msb_first [\shift_msb_first(a_width=64,resu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=12,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=3,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=2,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_8.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(length=3)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(length=2)\]
Compiling architecture synth of entity floating_point_v7_1_8.fix_to_flt_conv_exp [\fix_to_flt_conv_exp(c_xdevicefa...]
Compiling architecture synth of entity floating_point_v7_1_8.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture struct of entity floating_point_v7_1_8.fix_to_flt_conv [\fix_to_flt_conv(c_xdevicefamily...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8_viv [\floating_point_v7_1_8_viv(c_xde...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8 [\floating_point_v7_1_8(c_xdevice...]
Compiling architecture clahe_top_ap_uitofp_4_no_dsp_32_arch of entity xil_defaultlib.clahe_top_ap_uitofp_4_no_dsp_32 [clahe_top_ap_uitofp_4_no_dsp_32_...]
Compiling module xil_defaultlib.clahe_top_uitofp_32ns_32_6_1(ID=...
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=23,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="ki...]
Compiling architecture synth of entity floating_point_v7_1_8.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_8.special_detect [\special_detect(a_fw=24,op_delay...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_to_flt_conv_exp [\flt_to_flt_conv_exp(r_w=64,r_ew...]
Compiling architecture synth of entity floating_point_v7_1_8.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_to_flt_conv [\flt_to_flt_conv(c_xdevicefamily...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8_viv [\floating_point_v7_1_8_viv(c_xde...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8 [\floating_point_v7_1_8(c_xdevice...]
Compiling architecture clahe_top_ap_fpext_0_no_dsp_32_arch of entity xil_defaultlib.clahe_top_ap_fpext_0_no_dsp_32 [clahe_top_ap_fpext_0_no_dsp_32_d...]
Compiling module xil_defaultlib.clahe_top_fpext_32ns_64_2_1(ID=1...
Compiling module xil_defaultlib.clahe_top_sdiv_11ns_17s_16_15_se...
Compiling module xil_defaultlib.clahe_top_sdiv_11ns_17s_16_15_se...
Compiling module xil_defaultlib.clahe_top_sdiv_11ns_17s_16_15_se...
Compiling module xil_defaultlib.calc_lut_body_stream
Compiling module xil_defaultlib.dataflow_in_loop_out
Compiling module xil_defaultlib.calc_lut_stream
Compiling module xil_defaultlib.interpolation_stream_ind1_p_rom
Compiling module xil_defaultlib.interpolation_stream_ind1_p(Data...
Compiling module xil_defaultlib.interpolation_stream_ind2_p_rom
Compiling module xil_defaultlib.interpolation_stream_ind2_p(Data...
Compiling module xil_defaultlib.interpolation_stream_xa1_p_rom
Compiling module xil_defaultlib.interpolation_stream_xa1_p(DataW...
Compiling module xil_defaultlib.interpolation_stream_xa_p_rom
Compiling module xil_defaultlib.interpolation_stream_xa_p(DataWi...
Compiling module xil_defaultlib.interpolation_stream_buf_0_0_ram
Compiling module xil_defaultlib.interpolation_stream_buf_0_0(Dat...
Compiling module xil_defaultlib.saturate_cast
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_8.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture rtl of entity floating_point_v7_1_8.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_8.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_8.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(adreg=0,alumodereg=0,ca...]
Compiling architecture rtl of entity floating_point_v7_1_8.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_8.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=10)\]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_8.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_8.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_8.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_8.compare [\compare(c_xdevicefamily="zynq",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=9)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=2,length=2,fast_inp...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(length=2,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=23)\]
Compiling architecture synth of entity floating_point_v7_1_8.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_8.flt_add [\flt_add(c_xdevicefamily="zynq",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8_viv [\floating_point_v7_1_8_viv(c_xde...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8 [\floating_point_v7_1_8(c_xdevice...]
Compiling architecture clahe_top_ap_fadd_3_full_dsp_32_arch of entity xil_defaultlib.clahe_top_ap_fadd_3_full_dsp_32 [clahe_top_ap_fadd_3_full_dsp_32_...]
Compiling module xil_defaultlib.clahe_top_fadd_32ns_32ns_32_5_fu...
Compiling architecture rtl of entity floating_point_v7_1_8.flt_add [\flt_add(c_xdevicefamily="zynq",...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8_viv [\floating_point_v7_1_8_viv(c_xde...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8 [\floating_point_v7_1_8(c_xdevice...]
Compiling architecture clahe_top_ap_fsub_3_full_dsp_32_arch of entity xil_defaultlib.clahe_top_ap_fsub_3_full_dsp_32 [clahe_top_ap_fsub_3_full_dsp_32_...]
Compiling module xil_defaultlib.clahe_top_fsub_32ns_32ns_32_5_fu...
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=31,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=32)\]
Compiling architecture struct of entity floating_point_v7_1_8.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_8.delay [\delay(width=4)\]
Compiling architecture rtl of entity floating_point_v7_1_8.norm_zero_det [\norm_zero_det(data_width=7,norm...]
Compiling architecture rtl of entity floating_point_v7_1_8.lead_zero_encode [\lead_zero_encode(c_xdevicefamil...]
Compiling architecture rtl of entity floating_point_v7_1_8.shift_msb_first [\shift_msb_first(a_width=32,resu...]
Compiling architecture rtl of entity floating_point_v7_1_8.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture synth of entity floating_point_v7_1_8.fix_to_flt_conv_exp [\fix_to_flt_conv_exp(c_xdevicefa...]
Compiling architecture struct of entity floating_point_v7_1_8.fix_to_flt_conv [\fix_to_flt_conv(c_xdevicefamily...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8_viv [\floating_point_v7_1_8_viv(c_xde...]
Compiling architecture xilinx of entity floating_point_v7_1_8.floating_point_v7_1_8 [\floating_point_v7_1_8(c_xdevice...]
Compiling architecture clahe_top_ap_sitofp_4_no_dsp_32_arch of entity xil_defaultlib.clahe_top_ap_sitofp_4_no_dsp_32 [clahe_top_ap_sitofp_4_no_dsp_32_...]
Compiling module xil_defaultlib.clahe_top_sitofp_32ns_32_6_1(ID=...
Compiling module xil_defaultlib.clahe_top_mux_164_8_1_1(ID=1,din...
Compiling module xil_defaultlib.interpolation_stream
Compiling module xil_defaultlib.stream2axis
Compiling module xil_defaultlib.fifo_w8_d180_A
Compiling module xil_defaultlib.fifo_w8_d259200_A
Compiling module xil_defaultlib.fifo_w8_d2_A_shiftReg
Compiling module xil_defaultlib.fifo_w8_d2_A
Compiling module xil_defaultlib.start_for_calc_lut_stream_U0_shi...
Compiling module xil_defaultlib.start_for_calc_lut_stream_U0
Compiling module xil_defaultlib.start_for_interpolation_stream_U...
Compiling module xil_defaultlib.start_for_interpolation_stream_U...
Compiling module xil_defaultlib.start_for_stream2axis_U0_shiftRe...
Compiling module xil_defaultlib.start_for_stream2axis_U0
Compiling module xil_defaultlib.clahe_top
Compiling module xil_defaultlib.fifo(DEPTH=2073600)
Compiling module xil_defaultlib.AESL_axi_s_src
Compiling module xil_defaultlib.fifo(DEPTH=2073600,WIDTH=1)
Compiling module xil_defaultlib.AESL_axi_s_dst
Compiling module xil_defaultlib.AESL_axi_slave_AXILiteS
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detect_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_report_unit(PROC_N...
Compiling module xil_defaultlib.AESL_deadlock_detector_1
Compiling module xil_defaultlib.apatb_clahe_top_top
Compiling module work.glbl
Built simulation snapshot clahe_top


****** Webtalk v2019.1.3 (64-bit)
 **** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
 **** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


source /home/hlab/kokihonda/clahe_fpga/solution1/sim/verilog/xsim.dir/clahe_top/webtalk/xsim_webtalk.tcl -notrace
webtalk_transmit: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:06 . Memory (MB): peak = 489.559 ; gain = 0.000 ; free physical = 132626 ; free virtual = 164099" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:39:05.373+0900" type="Warning"/>
<logs message="WARNING: [VRFC 10-3499] library name 'floating_point_v7_1_8' of instantiated unit conflicts with visible identifier [/home/hlab/kokihonda/clahe_fpga/solution1/sim/verilog/ip/xil_defaultlib/clahe_top_ap_fsub_3_full_dsp_32.vhd:201]" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:38:45.408+0900" type="Warning"/>
<logs message="WARNING: [VRFC 10-3499] library name 'floating_point_v7_1_8' of instantiated unit conflicts with visible identifier [/home/hlab/kokihonda/clahe_fpga/solution1/sim/verilog/ip/xil_defaultlib/clahe_top_ap_fadd_3_full_dsp_32.vhd:201]" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:38:44.505+0900" type="Warning"/>
<logs message="WARNING: [VRFC 10-3499] library name 'floating_point_v7_1_8' of instantiated unit conflicts with visible identifier [/home/hlab/kokihonda/clahe_fpga/solution1/sim/verilog/ip/xil_defaultlib/clahe_top_ap_fpext_0_no_dsp_32.vhd:190]" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:38:42.378+0900" type="Warning"/>
<logs message="WARNING: [VRFC 10-3499] library name 'floating_point_v7_1_8' of instantiated unit conflicts with visible identifier [/home/hlab/kokihonda/clahe_fpga/solution1/sim/verilog/ip/xil_defaultlib/clahe_top_ap_uitofp_4_no_dsp_32.vhd:196]" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:38:39.131+0900" type="Warning"/>
<logs message="WARNING: [VRFC 10-3499] library name 'floating_point_v7_1_8' of instantiated unit conflicts with visible identifier [/home/hlab/kokihonda/clahe_fpga/solution1/sim/verilog/ip/xil_defaultlib/clahe_top_ap_fmul_2_max_dsp_32.vhd:201]" projectName="clahe_fpga" solutionName="solution1" date="2020-11-28T16:38:38.288+0900" type="Warning"/>
</simLog>
<mgLog/>
<packageLog/>
<csimLog/>
</logs>
</warningLogs>
</vivadoHLSLog:LogRoot>