Custom assembly language and Instruction Set Architecture Implementation in FPGA

Custom 16-bit assembly language and instruction set architecture to implement hardware multiplication on a DE-115 FPGA.

This project has been aimed to create a hardware and software multiplier capable of taking two signed 16-bit integers from I/O, multiplying them, and then returning them to I/O.

• Principles of Operation
• VHDL source code
• Assembler and emulator
• High-level language representation

Instruction Set Architecture closely follows the MIPS architecture.

Hardware synthesis is written in VHDL, assembler and emulator are written in python, and high-level language idea sketch is written in C++.