Demonstration on using a Soft Core (VexRiscv) built with LiTex in a Colorlight 5A-7B (ECP5). This demo is based on lab004 of fpga_101 repository.

• push button is used as reset
• led is used for led demo in firmware
• UART use (arbitrary) J1 pins 1 & 2

• openFPGALoader
• LiteX and Migen tools (see fpga_101 README for install everything).
• yosys, nextpnr and prjtrellis

• ColorLight has no on-board JTAG adapter, so user must solder a pinheader (J27 for JTAG signals, J33 for VCC and J34 for GND) and connect an external probe (see. chubby75);
• level shifter 74HC245T are used between FPGA and Jx connectors. To be able to use corresponding pins in bidirectional mode and in 3.3V instead 5V, buffer must be desoldered, and replace or just bypass. To have, a partial, access to J1, buffer U28 must be dropped (see next figure);
• an USB <-> serial converter must be used to have access to serial interface

U28 without buffer and with direct connection between input and output.

Just:

./base.py --build

cd firmware && make

see lab004 for more details.

./base.py --load [--cable yourCable]

where yourCable depends on your JTAG probe. If --cable is not provided openFPGALoader will uses ft2232` generic interface.

lxterm /dev/ttyUSBX --kernel firmware/firmware.bin

where ttyUSBX is your USB <-> UART converter device.

serialboot

To start the blink led use command

led