Merge pull request #46 from xdslproject/emilien/xdsl-bump

Bump xDSL & MLIR, update codebase.
xdslproject · Dec 20, 2023 · f502922 · f502922
2 parents 60cf743 + adfe3cc
commit f502922
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Showing 12 changed files with 40 additions and 36 deletions.
diff --git a/.github/workflows/ci-mlir-mpi.yml b/.github/workflows/ci-mlir-mpi.yml
@@ -20,8 +20,8 @@ on:
 
 jobs:
   build:
-    runs-on: ubuntu-20.04
-    container: papychacal/xdsl-llvm:04fc02e583b06b846315904a55af9c273c8b20b9
+    runs-on: ubuntu-latest
+    container: papychacal/xdsl-llvm:98e674c9f16d677d95c67bc130e267fae331e43c
     steps:
     - name: Checkout Devito
       uses: actions/checkout@v3
@@ -38,10 +38,10 @@ jobs:
       run: |
         pip install -e .[tests]
         pip install mpi4py
-        pip install git+https://github.com/xdslproject/xdsl@2825897b87443c9369abf89871f4721e2fce2da9
+        pip install git+https://github.com/xdslproject/xdsl@5500ff6d82d1a920b369615292ba507ecbf92fc9
 
     - name: Test with MPI
       run: |
         # Add mlir-opt to the path
         export PATH=/xdsl-sc/llvm-project/build/bin/:$PATH
-        pytest -m "parallel" -k "not adjoint" tests/test_xdsl_*
+        pytest -m "parallel" -k "not adjoint" tests/test_xdsl_*
diff --git a/.github/workflows/ci-mlir.yml b/.github/workflows/ci-mlir.yml
@@ -21,7 +21,7 @@ on:
 jobs:
   build:
     runs-on: ubuntu-latest
-    container: papychacal/xdsl-llvm:04fc02e583b06b846315904a55af9c273c8b20b9
+    container: papychacal/xdsl-llvm:98e674c9f16d677d95c67bc130e267fae331e43c
     steps:
     - name: Checkout Devito
       uses: actions/checkout@v3
@@ -38,8 +38,8 @@ jobs:
       run: |
         pip install -e .[tests]
         pip install mpi4py
-        pip install git+https://github.com/xdslproject/xdsl@2825897b87443c9369abf89871f4721e2fce2da9
-
+        pip install git+https://github.com/xdslproject/xdsl@5500ff6d82d1a920b369615292ba507ecbf92fc9
+        
     - name: Test no-MPI, no-Openmp
       run: |
         export DEVITO_MPI=0

diff --git a/devito/core/cpu.py b/devito/core/cpu.py
@@ -861,7 +861,8 @@ def generate_XDSL_CPU_PIPELINE(nb_tiled_dims):
     passes = [
         "stencil-shape-inference",
         f"convert-stencil-to-ll-mlir{{{generate_tiling_arg(nb_tiled_dims)}}}",
-        "printf-to-llvm"
+        "printf-to-llvm",
+        "canonicalize"
     ]
 
     return generate_pipeline(passes)
@@ -879,12 +880,13 @@ def generate_XDSL_CPU_noop_PIPELINE():
 
 def generate_XDSL_MPI_PIPELINE(decomp, nb_tiled_dims):
     passes = [
-        f"dmp-decompose{decomp}",
+        f"distribute-stencil{decomp}",
         "canonicalize-dmp",
         f"convert-stencil-to-ll-mlir{{{generate_tiling_arg(nb_tiled_dims)}}}",
         "dmp-to-mpi{mpi_init=false}",
         "lower-mpi",
-        "printf-to-llvm"
+        "printf-to-llvm",
+        "canonicalize"
     ]
 
     return generate_pipeline(passes)

diff --git a/devito/core/gpu.py b/devito/core/gpu.py
@@ -3,6 +3,7 @@
 from io import StringIO
 
 import numpy as np
+from devito.arch.archinfo import get_nvidia_cc
 
 from devito.core.operator import CoreOperator, CustomOperator, ParTile
 
@@ -545,7 +546,8 @@ def generate_XDSL_GPU_PIPELINE():
         "stencil-shape-inference",
         "convert-stencil-to-ll-mlir{target=gpu}",
         "reconcile-unrealized-casts",
-        "printf-to-llvm"
+        "printf-to-llvm",
+        "canonicalize"
     ]
 
     return generate_pipeline(passes)
@@ -564,7 +566,7 @@ def generate_MLIR_GPU_PIPELINE(block_sizes):
         "fold-memref-alias-ops",
         "gpu-launch-sink-index-computations",
         "gpu-kernel-outlining",
-        "canonicalize{{region-simplify}}",
+        "canonicalize{region-simplify}",
         "cse",
         "fold-memref-alias-ops",
         "expand-strided-metadata",
@@ -574,14 +576,16 @@ def generate_MLIR_GPU_PIPELINE(block_sizes):
         "func.func(gpu-async-region)",
         "canonicalize",
         "cse",
-        "convert-arith-to-llvm{{index-bitwidth=64}}",
+        "convert-arith-to-llvm{index-bitwidth=64}",
         "convert-scf-to-cf",
-        "convert-cf-to-llvm{{index-bitwidth=64}}",
+        "convert-cf-to-llvm{index-bitwidth=64}",
         "canonicalize",
         "cse",
-        "convert-func-to-llvm{{use-bare-ptr-memref-call-conv}}",
-        "gpu.module(convert-gpu-to-nvvm,reconcile-unrealized-casts,canonicalize,gpu-to-cubin)",  # noqa
+        "convert-func-to-llvm{use-bare-ptr-memref-call-conv}",
+        f"nvvm-attach-target{{O=3 ftz fast chip=sm_{get_nvidia_cc()}}}",
+        "gpu.module(convert-gpu-to-nvvm,canonicalize,cse)",
         "gpu-to-llvm",
+        "gpu-module-to-binary",
         "canonicalize",
         "cse)"
     ]

diff --git a/devito/ir/ietxdsl/cluster_to_ssa.py b/devito/ir/ietxdsl/cluster_to_ssa.py
@@ -188,7 +188,7 @@ def _visit_math_nodes(self, node: Expr) -> SSAValue:
             else:
                 raise ValueError("Expected float or int as pow args!")
 
-            op = op_cls.get(base, ex)
+            op = op_cls(base, ex)
             self.block.add_op(op)
             return op.result
         # Handle Mod
@@ -367,7 +367,7 @@ def match_and_rewrite(self, op: func.FuncOp, rewriter: PatternRewriter):
         assert ret is not None
 
         rewriter.insert_op_before([
-            timers := iet_ssa.LoadSymbolic.get('timers', llvm.LLVMPointerType.typed(builtin.f64)),
+            timers := iet_ssa.LoadSymbolic.get('timers', llvm.LLVMPointerType.opaque()),
             t1 := func.Call('timer_end', [t0], [builtin.f64]),
             llvm.StoreOp(t1, timers),
         ], ret)
@@ -441,7 +441,7 @@ def match_and_rewrite(self, op: iet_ssa.Stencil, rewriter: PatternRewriter, /):
                     stencil.IndexAttr.get(*([0] * rank)),
                     stencil.IndexAttr.get(*op.shape),
                 ),
-                scf.Yield.get(op.output, *op.input_indices),
+                scf.Yield(op.output, *op.input_indices),
             ]
         )
 

diff --git a/devito/ir/ietxdsl/iet_ssa.py b/devito/ir/ietxdsl/iet_ssa.py
@@ -366,7 +366,7 @@ class For(IRDLOperation):
 
     subindices: IntAttr = attr_def(IntAttr)
 
-    properties: ArrayAttr[builtin.StringAttr] = attr_def(ArrayAttr[builtin.StringAttr])
+    _properties: ArrayAttr[builtin.StringAttr] = attr_def(ArrayAttr[builtin.StringAttr])
     pragmas: ArrayAttr[builtin.StringAttr] = attr_def(ArrayAttr[builtin.StringAttr])
 
     def subindice_ssa_vals(self) -> tuple[SSAValue, ...]:
@@ -382,7 +382,7 @@ def parallelism_property(self) -> str | None:
         Return either "parallel" or "sequential" (or None),
         depending on the properties present
         """
-        for attr in self.properties.data:
+        for attr in self._properties.data:
             if attr.data in ('parallel', 'sequential'):
                 return attr.data
         return None

diff --git a/devito/ir/ietxdsl/lowering.py b/devito/ir/ietxdsl/lowering.py
@@ -16,9 +16,9 @@ def match_and_rewrite(self, op: scf.For, rewriter: PatternRewriter, /):
         if isinstance(op.lb.type, builtin.IndexType):
             return
         for val in (op.lb, op.ub, op.step):
-            cast = arith.IndexCastOp.get(val, builtin.IndexType())
+            cast = arith.IndexCastOp(val, builtin.IndexType())
             rewriter.insert_op_before_matched_op(cast)
-            op.replace_operand(op.operands.index(val), cast.result)
+            op.operands[op.operands.index(val)] = cast.result
 
 
 class ConvertScfParallelArgsToIndex(RewritePattern):
@@ -41,9 +41,9 @@ def match_and_rewrite(self, op: scf.ParallelOp, rewriter: PatternRewriter,
         for val in (*op.lowerBound, *op.upperBound, *op.step):
             if isinstance(val.type, builtin.IndexType):
                 continue
-            cast = arith.IndexCastOp.get(val, builtin.IndexType())
+            cast = arith.IndexCastOp(val, builtin.IndexType())
             rewriter.insert_op_before_matched_op(cast)
-            op.replace_operand(op.operands.index(val), cast.result)
+            op.operands[op.operands.index(val)] = cast.result
 
 
 class ConvertForLoopVarToIndex(RewritePattern):
@@ -60,12 +60,12 @@ def match_and_rewrite(self, op: Operation, rewriter: PatternRewriter, /):
             # insert a cast from index to i64 at the start of the loop
 
             rewriter.insert_op_at_start(
-                i64_val := arith.IndexCastOp.get(loop_var, builtin.i64),
+                i64_val := arith.IndexCastOp(loop_var, builtin.i64),
                 block,
             )
 
             loop_var.replace_by(i64_val.result)
-            i64_val.replace_operand(0, loop_var)
+            i64_val.operands[0] = loop_var
 
 
 class LowerIetForToScfFor(RewritePattern):

diff --git a/fast/wave2d_b.py b/fast/wave2d_b.py
@@ -4,12 +4,12 @@
 
 from devito import (TimeFunction, Eq, Operator, solve, norm,
                     configuration, Grid)
-from fast.bench_utils import plot_2dfunc
 from devito.tools import as_tuple
 
 import argparse
-np.set_printoptions(threshold=np.inf)
+from fast.bench_utils import plot_2dfunc
 
+np.set_printoptions(threshold=np.inf)
 
 parser = argparse.ArgumentParser(description='Process arguments.')
 
@@ -28,7 +28,6 @@
 parser.add_argument("-xdsl", "--xdsl", default=False, type=bool, help="xDSL run")
 args = parser.parse_args()
 
-
 mpiconf = configuration['mpi']
 
 # Define a physical size

diff --git a/fast/wave3d_b.py b/fast/wave3d_b.py
@@ -4,12 +4,12 @@
 
 from devito import (TimeFunction, Eq, Operator, solve, norm,
                     configuration, Grid)
-from fast.bench_utils import plot_3dfunc
 from devito.tools import as_tuple
 
 import argparse
-np.set_printoptions(threshold=np.inf)
+from fast.bench_utils import plot_3dfunc
 
+np.set_printoptions(threshold=np.inf)
 
 parser = argparse.ArgumentParser(description='Process arguments.')
 
@@ -28,7 +28,6 @@
 parser.add_argument("-xdsl", "--xdsl", default=False, type=bool, help="xDSL run")
 args = parser.parse_args()
 
-
 mpiconf = configuration['mpi']
 
 # Define a physical size

diff --git a/requirements.txt b/requirements.txt
@@ -15,5 +15,5 @@ distributed<2022.10
 pytest>=3.6,<8.0
 pytest-runner
 pytest-cov
-xdsl>=0.11
+xdsl
 frozenlist<=1.4
diff --git a/tests/test_xdsl_iet.py b/tests/test_xdsl_iet.py
@@ -50,7 +50,7 @@ def test_powi():
 
     mod = ModuleOp([
         cst1 := Constant.from_int_and_width(1, i32),
-        ut1 := FPowIOp.get(cst1, cst1),
+        ut1 := FPowIOp(cst1, cst1),
     ])
 
 

diff --git a/xdsl_llvm.docker b/xdsl_llvm.docker
@@ -1,6 +1,6 @@
 FROM ubuntu:22.04 as build
 
-ARG mlirhash=04fc02e583b06b846315904a55af9c273c8b20b9
+ARG mlirhash=98e674c9f16d677d95c67bc130e267fae331e43c
 
 # base requirements
 RUN apt-get update \