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9 Open 13 Closed
9 Open 13 Closed
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Issues list

Translation entry eviction needs to be handled correctly bug
#22 opened Mar 15, 2018 by ymarathe
@ymarathe @s-naveena
Cache to cache transfer needs to be modeled bug
#14 opened Feb 7, 2018 by ymarathe
Coherence logic marks L2 line as modified on a *_WRITE bug question
#13 opened Feb 7, 2018 by ymarathe
1
Coherence logic broadcasts *_READ updates incorrectly bug
#12 opened Feb 7, 2018 by ymarathe
1
Build trace consumption logic into the simulator bug
#11 opened Feb 7, 2018 by ymarathe
Decide on number of outstanding misses at each level enhancement question
#7 opened Feb 6, 2018 by ymarathe
@ymarathe @nagendragd
Add instrumentation counters in each unit bug
#5 opened Feb 6, 2018 by ymarathe
RequestStatus is not propagated upstream in the cache hierarchy bug
#2 opened Feb 6, 2018 by ymarathe
Simulation progresses only if all cores->tick() is called bug
#1 opened Feb 6, 2018 by ymarathe
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