Zeptron - RISC-V CPU

Overview

Zeptron is a RISC-V compatible CPU with 5 pipeline stages. It is implemented in SystemVerilog and verified using riscof. The scripts use Modelsim to simulate the architectual tests supplied by riscof. The verification is done in a seperated repository Zeptron-riscof. The CPU supports the rv32i instruction set architecture.

Implementation Details

Test Utils Module

• Memory mapped at 0x100
• 0x100 address begin signature
• 0x104 address end signature
• 0x108 address if non zero -> dump signature and quit sim

Memory Model

• 0x000 - 0x100 not in Use
• 0x100 - 0x112 Test utilities module
• 0x112 - 0x200 not in Use
• 0x200 - 0xXXX code segment