Adding support for Microchip PIC32CX SG devices

hal: microchip: pic32cx:Adding support for Microchip PIC32CX SG devices
This is based on the hal atmel libraries as a starting point.

Signed-off-by: Michael Sherwood <Michael.Sherwood@microchip.com>

CMakeLists.txt

@@ -1,3 +1,5 @@
 add_subdirectory_ifdef(CONFIG_HAS_MEC_HAL mec)
 add_subdirectory_ifdef(CONFIG_HAS_MPFS_HAL mpfs)
 add_subdirectory_ifdef(CONFIG_HAS_MEC5_HAL mec5)
+zephyr_include_directories_ifdef(CONFIG_MPLABX include)
+add_subdirectory(mplabx)

README.md

@@ -0,0 +1,67 @@
+# Introduction
+
+The **hal_microchip** is a set of register definitions for Microchip PIC32C/PIC32M SoC's.
+The HAL is organized following the directory structure detailed below.
+
+## Directory Structure
+
+The directory is composed by six parts:
+```
+.
+├── mplabx
+├── include
+├── pinconfigs
+├── README.md
+├── scripts
+└── zephyr
+```
+
+ - MPLABX SoC specific include libraries.
+ - Includes specific for these platforms
+   - devicetree bindings
+ - [Pin definitions](pinconfigs/README.md)
+ - [Scripts](scripts/README.md) used for code generation
+ - ZephyrRTOS module directory (`zephyr`).
+ - This README file.
+
+# How to submit code
+
+Any contribution should follow the `How to submit code` using as premisses the
+[Zephyr Contribution Guidelines](https://docs.zephyrproject.org/latest/contribute/index.html).
+For more information about External Modules see
+[Modules Section](https://docs.zephyrproject.org/latest/develop/modules.html) in special
+[Submitting Changes to Modules](https://docs.zephyrproject.org/latest/develop/modules.html#submitting-changes-to-modules)
+
+
+## Repository specific guidelines
+
+ - When submitting an updated firmware library version, it is important to make
+   sure that the last firmware version will be merged. The library version is
+   used to be checked at [Microchip packs download site](http://packs.download.microchip.com/).
+ - When submitting an updated firmware library version the patchset already
+   applied should be rebased on top of the newer version.
+ - The patchset must be sent as an individual commit per SoC series to easy rebase.
+ - This repository is managed mainly on Linux. This means that changes should
+   be submitted using Linux LF format. Usually running a similar command to
+   `find * type f -print0 | xargs -0 dos2unix -k` should be enough.
+ - Make sure directory structure is respected.
+ - The `mplabx/[pic32cxsg]/include/<soc>/README` file should be updated accordingly.
+   If for some reason the file not exists it should be created.
+ - Directory names should be converted to lowercase.
+ - The recommendation is add **all fixups** in the `hal_atmel` instead on the
+   ZephyrRTOS project.
+
+The above are general guidelines and exceptions could happen. In this case, the
+exception should be addressed at review phase.
+
+## The standard API
+
+The PIC32C/PIC32M standard API define all information to access Microchip SoC's
+peripherals. This library does not have namespaces and prefixes which
+easily results in name collision with ZephyrRTOS core and libraries. To avoid
+that situation, macros, enum values and function names should follow two
+general rules:
+
+ - Public API functions must be prefixed with `pic32cxsg_` or .
+ - Public defines and enum values must be uppercase and prefixed with `PIC32CXSG_`
+   or .

include/dt-bindings/pinctrl/microchip_pic32cxsg_pinctrl.h

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+/*
+ * Copyright (c) 2024 Microchip
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DT_BINDINGS_PINCTRL_MICROCHIP_PIC32CXSG_PINCTRL_H_
+#define DT_BINDINGS_PINCTRL_MICROCHIP_PIC32CXSG_PINCTRL_H_
+
+/*
+ * @name Microchip PIC32CXSG gpio port list. (Uses Atmel SAM0 gpio)
+ * @{
+ */
+
+#define SAM_PINMUX_PORT_a		0U
+#define SAM_PINMUX_PORT_b		1U
+#define SAM_PINMUX_PORT_c		2U
+#define SAM_PINMUX_PORT_d		3U
+#define SAM_PINMUX_PORT_e		4U
+#define SAM_PINMUX_PORT_f		5U
+#define SAM_PINMUX_PORT_g		6U
+#define SAM_PINMUX_PORT_h		7U
+#define SAM_PINMUX_PORT_i		8U
+#define SAM_PINMUX_PORT_j		9U
+#define SAM_PINMUX_PORT_k		10U
+#define SAM_PINMUX_PORT_l		11U
+#define SAM_PINMUX_PORT_m		12U
+#define SAM_PINMUX_PORT_n		13U
+#define SAM_PINMUX_PORT_o		14U
+#define SAM_PINMUX_PORT_p		15U
+
+/** @} */
+
+/**
+ * @name Microchip PIC32CXSG peripheral list. (Uses Atmel SAM0 gpio)
+ * @{
+ */
+
+/** GPIO */
+#define SAM_PINMUX_PERIPH_gpio		0U
+/** Peripherals */
+#define SAM_PINMUX_PERIPH_a		0U
+#define SAM_PINMUX_PERIPH_b		1U
+#define SAM_PINMUX_PERIPH_c		2U
+#define SAM_PINMUX_PERIPH_d		3U
+#define SAM_PINMUX_PERIPH_e		4U
+#define SAM_PINMUX_PERIPH_f		5U
+#define SAM_PINMUX_PERIPH_g		6U
+#define SAM_PINMUX_PERIPH_h		7U
+#define SAM_PINMUX_PERIPH_i		8U
+#define SAM_PINMUX_PERIPH_j		9U
+#define SAM_PINMUX_PERIPH_k		10U
+#define SAM_PINMUX_PERIPH_l		11U
+#define SAM_PINMUX_PERIPH_m		12U
+#define SAM_PINMUX_PERIPH_n		13U
+/** Extra */
+#define SAM_PINMUX_PERIPH_x		0U
+/** System */
+#define SAM_PINMUX_PERIPH_s		0U
+/** LPM */
+#define SAM_PINMUX_PERIPH_lpm		0U
+/** Wake-up pin sources */
+#define SAM_PINMUX_PERIPH_wkup0		0U
+#define SAM_PINMUX_PERIPH_wkup1		1U
+#define SAM_PINMUX_PERIPH_wkup2		2U
+#define SAM_PINMUX_PERIPH_wkup3		3U
+#define SAM_PINMUX_PERIPH_wkup4		4U
+#define SAM_PINMUX_PERIPH_wkup5		5U
+#define SAM_PINMUX_PERIPH_wkup6		6U
+#define SAM_PINMUX_PERIPH_wkup7		7U
+#define SAM_PINMUX_PERIPH_wkup8		8U
+#define SAM_PINMUX_PERIPH_wkup9		9U
+#define SAM_PINMUX_PERIPH_wkup10	10U
+#define SAM_PINMUX_PERIPH_wkup11	11U
+#define SAM_PINMUX_PERIPH_wkup12	12U
+#define SAM_PINMUX_PERIPH_wkup13	13U
+#define SAM_PINMUX_PERIPH_wkup14	14U
+#define SAM_PINMUX_PERIPH_wkup15	15U
+/** @} */
+
+/**
+ * @name Microchip PIC32CXSG pin function list. (Uses Atmel SAM0 gpio)
+ * @{
+ */
+
+/** Selects pin to be used as GPIO */
+#define SAM_PINMUX_FUNC_gpio		0U
+/** Selects pin to be used as by some peripheral */
+#define SAM_PINMUX_FUNC_periph		1U
+/** Selects pin to be used as extra function */
+#define SAM_PINMUX_FUNC_extra		2U
+/** Selects pin to be used as system function */
+#define SAM_PINMUX_FUNC_system		3U
+/** Selects and configure pin to be used in Low Power Mode */
+#define SAM_PINMUX_FUNC_lpm		4U
+/** Selects and configure wake-up pin sources Low Power Mode */
+#define SAM_PINMUX_FUNC_wakeup		5U
+
+/** @} */
+
+/**
+ * @name Microchip PIC32CXSG pinmux bit field mask and positions. (Uses Atmel SAM0 gpio)
+ * @{
+ */
+
+/** Pinmux bit field position. */
+#define SAM_PINCTRL_PINMUX_POS  	(16U)
+/** Pinmux bit field mask. */
+#define SAM_PINCTRL_PINMUX_MASK 	(0xFFFF)
+
+/** Port field mask. */
+#define SAM_PINMUX_PORT_MSK		(0xFU)
+/** Port field position. */
+#define SAM_PINMUX_PORT_POS		(0U)
+/** Pin field mask. */
+#define SAM_PINMUX_PIN_MSK		(0x1FU)
+/** Pin field position. */
+#define SAM_PINMUX_PIN_POS		(SAM_PINMUX_PORT_POS + 4U)
+/** Function field mask. */
+#define SAM_PINMUX_FUNC_MSK		(0x7U)
+/** Function field position. */
+#define SAM_PINMUX_FUNC_POS		(SAM_PINMUX_PIN_POS + 5U)
+/** Peripheral field mask. */
+#define SAM_PINMUX_PERIPH_MSK		(0xFU)
+/** Peripheral field position. */
+#define SAM_PINMUX_PERIPH_POS		(SAM_PINMUX_FUNC_POS + 3U)
+
+/** @} */
+
+/**
+ * @brief Microchip PIC32CXSG pinmux bit field. (Uses Atmel SAM0 gpio)
+ * @anchor SAM_PINMUX
+ *
+ * Fields:
+ *
+ * -   0..3: port
+ * -   4..8: pin_num
+ * -  9..11: func
+ * - 12..15: pin_mux
+ *
+ * @param port    Port ('A'..'P')
+ * @param pin     Pin  (0..31)
+ * @param func    Function (GPIO, Peripheral, System, Extra, LPM - 0..4)
+ * @param pin_mux Peripheral based on the Function selected (0..15)
+ */
+#define SAM_PINMUX(port, pin_num, pin_mux, func)			  \
+	((((SAM_PINMUX_PORT_##port) & SAM_PINMUX_PORT_MSK)		  \
+	 << SAM_PINMUX_PORT_POS)					| \
+	 (((pin_num) & SAM_PINMUX_PIN_MSK)				  \
+	 << SAM_PINMUX_PIN_POS)						| \
+	 (((SAM_PINMUX_FUNC_##func) & SAM_PINMUX_FUNC_MSK)		  \
+	 << SAM_PINMUX_FUNC_POS)					| \
+	 (((SAM_PINMUX_PERIPH_##pin_mux) & SAM_PINMUX_PERIPH_MSK)	  \
+	 << SAM_PINMUX_PERIPH_POS))
+
+/**
+ * Obtain Pinmux value from pinctrl_soc_pin_t configuration.
+ *
+ * @param pincfg pinctrl_soc_pin_t bit field value.
+ */
+#define SAM_PINMUX_GET(pincfg) \
+	(((pincfg) >> SAM_PINCTRL_PINMUX_POS) & SAM_PINCTRL_PINMUX_MASK)
+
+#define SAM_PINMUX_PORT_GET(pincfg) \
+	((SAM_PINMUX_GET(pincfg) >> SAM_PINMUX_PORT_POS) \
+	 & SAM_PINMUX_PORT_MSK)
+
+#define SAM_PINMUX_PIN_GET(pincfg) \
+	((SAM_PINMUX_GET(pincfg) >> SAM_PINMUX_PIN_POS) \
+	 & SAM_PINMUX_PIN_MSK)
+
+#define SAM_PINMUX_FUNC_GET(pincfg) \
+	((SAM_PINMUX_GET(pincfg) >> SAM_PINMUX_FUNC_POS) \
+	 & SAM_PINMUX_FUNC_MSK)
+
+#define SAM_PINMUX_PERIPH_GET(pincfg) \
+	((SAM_PINMUX_GET(pincfg) >> SAM_PINMUX_PERIPH_POS) \
+	 & SAM_PINMUX_PERIPH_MSK)
+
+#endif  /* DT_BINDINGS_PINCTRL_MICROCHIP_PIC32CXSG_PINCTRL_H_ */