zephyrproject-rtos · scottwcpg · Oct 11, 2019
diff --git a/mec/common/regaccess.h b/mec/common/regaccess.h
@@ -29,33 +29,33 @@
 
 #include <stdint.h>
 
-#define MMCR32(a)   *((volatile uint32_t *)(uintptr_t)(a))
-#define MMCR16(a)   *((volatile uint16_t *)(uintptr_t)(a))
-#define MMCR8(a)    *((volatile uint8_t *)(uintptr_t)(a))
+#define MMCR32(a)   *((volatile uint32_t *)(a))
+#define MMCR16(a)   *((volatile uint16_t *)(a))
+#define MMCR8(a)    *((volatile uint8_t *)(a))
 
-#define MMCR_RD32(a, v)   v = *((volatile uint32_t *)(uintptr_t)(a))
-#define MMCR_RD16(a, v)   v = *((volatile uint16_t *)(uintptr_t)(a))
-#define MMCR_RD8(a, v)    v = *((volatile uint8_t *)(uintptr_t)(a))
+#define MMCR_RD32(a, v)   v = *((volatile uint32_t *)(a))
+#define MMCR_RD16(a, v)   v = *((volatile uint16_t *)(a))
+#define MMCR_RD8(a, v)    v = *((volatile uint8_t *)(a))
 
-#define MMCR_WR32(a, d)   *((volatile uint32_t *)(uintptr_t)(a)) = (uint32_t)(d)
-#define MMCR_WR16(a, h)   *((volatile uint16_t *)(uintptr_t)(a)) = (uint16_t)(h)
-#define MMCR_WR8(a, b)    *((volatile uint8_t *)(uintptr_t)(a)) = (uint8_t)(b)
+#define MMCR_WR32(a, d)   *((volatile uint32_t *)(a)) = (uint32_t)(d)
+#define MMCR_WR16(a, h)   *((volatile uint16_t *)(a)) = (uint16_t)(h)
+#define MMCR_WR8(a, b)    *((volatile uint8_t *)(a)) = (uint8_t)(b)
 
-#define REG32(a)    *((volatile uint32_t *)(uintptr_t)(a))
-#define REG16(a)    *((volatile uint16_t *)(uintptr_t)(a))
-#define REG8(a)     *((volatile uint8_t *)(uintptr_t)(a))
+#define REG32(a)    *((volatile uint32_t *)(a))
+#define REG16(a)    *((volatile uint16_t *)(a))
+#define REG8(a)     *((volatile uint8_t *)(a))
 
-#define REG32W(a, d)    *((volatile uint32_t *)(uintptr_t)(a)) = (uint32_t)(d)
-#define REG16W(a, h)    *((volatile uint16_t *)(uintptr_t)(a)) = (uint16_t)(h)
-#define REG8W(a, b)     *((volatile uint8_t *)(uintptr_t)(a)) = (uint8_t)(b)
+#define REG32W(a, d)    *((volatile uint32_t *)(a)) = (uint32_t)(d)
+#define REG16W(a, h)    *((volatile uint16_t *)(a)) = (uint16_t)(h)
+#define REG8W(a, b)     *((volatile uint8_t *)(a)) = (uint8_t)(b)
 
-#define REG32R(a, d)    (d) = *(volatile uint32_t *)(uintptr_t)(a)
-#define REG16R(a, h)    (h) = *(volatile uint16_t *)(uintptr_t)(a)
-#define REG8R(a, b)     (b) = *(volatile uint8_t *)(uintptr_t)(a)
+#define REG32R(a, d)    (d) = *(volatile uint32_t *)(a)
+#define REG16R(a, h)    (h) = *(volatile uint16_t *)(a)
+#define REG8R(a, b)     (b) = *(volatile uint8_t *)(a)
 
-#define REG32_OFS(a, ofs)   *(volatile uint32_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
-#define REG16_OFS(a, ofs)   *(volatile uint16_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
-#define REG8_OFS(a, ofs)    *(volatile uint8_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
+#define REG32_OFS(a, ofs)   *(volatile uint32_t *)((uint32_t)(a) + (uint32_t)(ofs))
+#define REG16_OFS(a, ofs)   *(volatile uint16_t *)((uint32_t)(a) + (uint32_t)(ofs))
+#define REG8_OFS(a, ofs)    *(volatile uint8_t *)((uint32_t)(a) + (uint32_t)(ofs))
 
 
 #endif // #ifndef _REGACCESS_H
diff --git a/mec/mec1501/MEC1501hsz.h b/mec/mec1501/MEC1501hsz.h
@@ -149,7 +149,7 @@ typedef enum IRQn {
 	PHOT_IRQn = 87,	/* GIRQ17 b[17] */
 	/* reserved gap 88-89 */
 	SPISLV_IRQn = 90,	/* GIRQ18 b[0] */
-	QMSPI_IRQn = 91,	/* GIRQ18 b[1] */
+	QMSPI0_IRQn = 91,	/* GIRQ18 b[1] */
 	/* reserved gap 92-99 */
 	PS2_0_ACT_IRQn = 100,	/* GIRQ18 b[10] */
 	PS2_1_ACT_IRQn = 101,	/* GIRQ18 b[11] */
@@ -480,6 +480,10 @@ typedef enum IRQn {
 #define B32TMR1_REGS	((BTMR_Type *) B32TMR1_BASE)
 #define CCT_REGS	((CCT_Type *) (CCT_BASE))
 
+#define DMA_MAX_CHAN	12u
+/* Complete DMA block */
+#define DMA_REGS 	((DMA_Type *) DMA_BASE)
+/* DMA Main only */
 #define DMAM_REGS       ((DMAM_Type *) DMA_BASE)
 /* Individual DMA channels */
 #define DMA0_REGS       ((DMA_CHAN_ALU_Type *)(DMA_CHAN_BASE(0)))
@@ -526,6 +530,7 @@ typedef enum IRQn {
 
 #define RTMR_REGS       ((RTMR_Type *) RTMR_BASE)
 
+#define ADC_MAX_CHAN	8u
 #define ADC_REGS	((ADC_Type *) ADC_BASE)
 
 #define TFDP_REGS	((TFDP_Type *) TFDP_BASE)
@@ -548,6 +553,7 @@ typedef enum IRQn {
 #define LED1_REGS       ((LED_Type *) LED1_BASE)
 #define LED2_REGS       ((LED_Type *) LED2_BASE)
 
+#define ECIA_NUM_GIRQS	(26u-8u+1)
 #define ECIA_REGS       ((ECIA_Type *) ECIA_BASE)
 #define GIRQ08_REGS     ((GIRQ_Type *) ECIA_BASE)
 #define GIRQ09_REGS     ((GIRQ_Type *) ((ECIA_BASE) + 0x14))
@@ -571,15 +577,17 @@ typedef enum IRQn {
 
 #define ECS_REGS        ((ECS_Type *) ECS_BASE)
 
-#define QMSPI_REGS      ((QMSPI_Type *) QMSPI_BASE)
+#define QMSPI_0_MAX_DESCR	16u
+#define QMSPI_0_REGS		((QMSPI_Type *) QMSPI_BASE)
 
 #define PCR_REGS        ((PCR_Type *) PCR_BASE)
 
-#define GPIO_CTRL_REGS      ((GPIO_CTRL_Type *)(GPIO_CTRL_BASE))
-#define GPIO_CTRL2_REGS     ((GPIO_CTRL2_Type *)(GPIO_CTRL2_BASE))
-#define GPIO_PARIN_REGS     ((GPIO_PARIN_Type *)(GPIO_PARIN_BASE))
-#define GPIO_PAROUT_REGS    ((GPIO_PAROUT_Type *)(GPIO_PAROUT_BASE))
-#define GPIO_LOCK_REGS      ((GPIO_LOCK_Type *)(GPIO_LOCK_BASE))
+#define GPIO_REGS		((GPIO_Type *)(GPIO_BASE))
+#define GPIO_CTRL_REGS		((GPIO_CTRL_Type *)(GPIO_CTRL_BASE))
+#define GPIO_CTRL2_REGS		((GPIO_CTRL2_Type *)(GPIO_CTRL2_BASE))
+#define GPIO_PARIN_REGS		((GPIO_PARIN_Type *)(GPIO_PARIN_BASE))
+#define GPIO_PAROUT_REGS	((GPIO_PAROUT_Type *)(GPIO_PAROUT_BASE))
+#define GPIO_LOCK_REGS		((GPIO_LOCK_Type *)(GPIO_LOCK_BASE))
 
 #define MBOX_REGS       ((MBOX_Type *)(MBOX_BASE))
 

diff --git a/mec/mec1501/component/adc.h b/mec/mec1501/component/adc.h
@@ -157,12 +157,22 @@
 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK	(0x3fful << 7)
 #define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT	(0x202ul << 7)
 
-/* Register interface */
-#define MCHP_ADC_CH_NUM(n) ((n) & MCHP_ADC_MAX_CHAN_MASK)
-#define MCHP_ADC_CH_OFS(n) (MCHP_ADC_CH_NUM(n) << 2)
-#define MCHP_ADC_CH_ADDR(n) (MCHP_ADC_BASE_ADDR + MCHP_ADC_CH_OFS(n))
-
-#define MCHP_ADC_RD_CHAN(n) REG32(MCHP_ADC_CH_ADDR(n))
+/*
+ * Register interface
+ * ba is base address of ADC register block.
+ */
+#define MCHP_ADC_CTRL(ba)		REG32((ba))
+#define MCHP_ADC_DELAY32(ba)		REG32((ba) + 4u)
+#define MCHP_ADC_START_DELAY(ba)	REG16((ba) + 4u)
+#define MCHP_ADC_REPEAT_DELAY(ba)	REG16((ba) + 6u)
+#define MCHP_ADC_STATUS(ba)		REG32((ba) + 8u)
+#define MCHP_ADC_SINGLE_EN(ba)		REG32((ba) + 0x0Cu)
+#define MCHP_ADC_REPEAT_EN(ba)		REG32((ba) + 0x10u)
+#define MCHP_ADC_RD_CHAN(ba, ch)	REG16((ba) + 0x14u + ((ch) * 4))
+#define MCHP_ADC_CONFIG(ba)		REG32((ba) + 0x7Cu)
+#define MCHP_ADC_VREF_CHAN(ba)		REG32((ba) + 0x80u)
+#define MCHP_ADC_VREF_CTRL(ba)		REG32((ba) + 0x84u)
+#define MCHP_ADC_SARADC_CTRL(ba)	REG32((ba) + 0x88u)
 
 /**
   * @brief Analog to Digital Converter Registers (ADC)
@@ -173,14 +183,7 @@ typedef struct adc_regs {
 	__IOM uint32_t STATUS; /*!< (@ 0x0008) ADC Status */
 	__IOM uint32_t SINGLE; /*!< (@ 0x000C) ADC Single */
 	__IOM uint32_t REPEAT; /*!< (@ 0x0010) ADC Repeat */
-	__IOM uint32_t RDCH0; /*!< (@ 0x0014) ADC Chan0 Reading */
-	__IOM uint32_t RDCH1; /*!< (@ 0x0018) ADC Chan1 Reading */
-	__IOM uint32_t RDCH2; /*!< (@ 0x001C) ADC Chan2 Reading */
-	__IOM uint32_t RDCH3; /*!< (@ 0x0020) ADC Chan3 Reading */
-	__IOM uint32_t RDCH4; /*!< (@ 0x0024) ADC Chan4 Reading */
-	__IOM uint32_t RDCH5; /*!< (@ 0x0028) ADC Chan5 Reading */
-	__IOM uint32_t RDCH6; /*!< (@ 0x002C) ADC Chan6 Reading */
-	__IOM uint32_t RDCH7; /*!< (@ 0x0030) ADC Chan7 Reading */
+	__IOM uint32_t RDCH[MCHP_ADC_MAX_CHAN]; /*!< (@ 0x0014 - 0x0030) ADC Chan 0-7 reading value */
 	uint8_t RSVD1[0x7C - 0x34];
 	__IOM uint32_t CONFIG; /*!< (@ 0x007C) ADC Configuration */
 	__IOM uint32_t VREF_CHAN_SEL; /*!< (@ 0x0080) ADC Vref Channel Sel. */

diff --git a/mec/mec1501/component/dma.h b/mec/mec1501/component/dma.h
@@ -40,6 +40,7 @@
 #include "regaccess.h"
 
 #define MCHP_NUM_DMA_CHANNELS	12ul
+#define MCHP_DMA_CHAN_BITMAP	0xffful
 
 #define MCHP_DMA_BLOCK_BASE_ADDR	0x40002400ul
 #define MCHP_DMA_CHAN_OFFSET		0x40ul
@@ -48,7 +49,10 @@
 	((MCHP_DMA_BLOCK_BASE_ADDR) + (MCHP_DMA_CHAN_OFFSET))
 
 #define MCHP_DMA_CHAN_ADDR(n) ((uintptr_t)(MCHP_DMA_CHAN0_ADDR) +\
-	((uintptr_t)(n) << MCHP_DMA_OFFSET_POF2))
+			       ((uintptr_t)(n) << MCHP_DMA_OFFSET_POF2))
+
+#define MCHP_DMA_CH_ADDR(ba, n) ((uintptr_t)(ba) +\
+				 ((uintptr_t)(n) << MCHP_DMA_OFFSET_POF2))
 
 /*
  * DMA block PCR register and bit
@@ -158,7 +162,7 @@
 #define MCHP_DMA_DEVNUM_SMB4_RX		9ul
 #define MCHP_DMA_DEVNUM_QMSPI_TX	10ul
 #define MCHP_DMA_DEVNUM_QMSPI_RX	11ul
-#define MCHP_DMA_DEVNUM_MAX		 12ul
+#define MCHP_DMA_DEVNUM_MAX		12ul
 
 #define MCHP_DMA_CHAN_REG_BLEN		0x40ul
 
@@ -187,14 +191,9 @@
 /*
  * DMA Main Register Access
  */
-#define MCHP_DMAM_CTRL() \
-	REG8_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_CTRL_OFS)
-
-#define MCHP_DMAM_PKT_RO() \
-	REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_PKT_RO_OFS)
-
-#define MCHP_DMAM_FSM_RO() \
-	REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_FSM_RO_OFS)
+#define MCHP_DMAM_CTRL(ba) REG8_OFS(ba, MCHP_DMAM_CTRL_OFS)
+#define MCHP_DMAM_PKT_RO(ba) REG32_OFS(ba, MCHP_DMAM_PKT_RO_OFS)
+#define MCHP_DMAM_FSM_RO(ba) REG32_OFS(ba, MCHP_DMAM_FSM_RO_OFS)
 
 /*
  * DMA channel register offsets
@@ -323,6 +322,22 @@
 #define MCHP_DMA_ALU_STS_RO_BA(chba) \
 	REG8_OFS(chba, MCHP_DMA_ALU_STS_RO_OFS)
 
+
+/*
+ * Register access given base address of DMA block and channel number
+ */
+#define MCHP_DMA_CH_ACT(ba, n) REG8_OFS(MCHP_DMA_CH_ADDR(ba, n), 0)
+#define MCHP_DMA_CH_MSTART(ba, n) REG32_OFS(MCHP_DMA_CH_ADDR(ba, n), 4)
+#define MCHP_DMA_CH_MEND(ba, n) REG32_OFS(MCHP_DMA_CH_ADDR(ba, n), 8)
+#define MCHP_DMA_CH_DSTART(ba, n) REG32_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x0c)
+#define MCHP_DMA_CH_CTRL(ba, n) REG32_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x10)
+#define MCHP_DMA_CH_ISTS(ba, n) REG8_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x14)
+#define MCHP_DMA_CH_IEN(ba, n) REG8_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x18)
+#define MCHP_DMA_CH_FSM_RO(ba, n) REG32_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x1c)
+#define MCHP_DMA_CH_ALU_EN(ba, n) REG8_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x20)
+#define MCHP_DMA_CH_ALU_DATA(ba, n) REG32_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x24)
+#define MCHP_DMA_CH_ALU_STS_RO(ba, n) REG8_OFS(MCHP_DMA_CH_ADDR(ba, n), 0x28)
+
 /*
  * Channel Activate, Offset 0x00, R/W
  */
@@ -355,6 +370,7 @@
 #define MCHP_DMA_C_BUSY_STS_POS		5u
 #define MCHP_DMA_C_BUSY_STS		(1UL << 5)
 #define MCHP_DMA_C_DIR_POS		8u
+#define MCHP_DMA_C_DIR_MASK		(1ul << 8)
 #define MCHP_DMA_C_DEV2MEM		(0UL << 8)
 #define MCHP_DMA_C_MEM2DEV		(1UL << 8)
 #define MCHP_DMA_C_DEV_NUM_POS		9u
@@ -366,6 +382,8 @@
 #define MCHP_DMA_C_INCR_DEV		(1UL << 17)
 #define MCHP_DMA_C_LOCK_CHAN		(1UL << 18)
 #define MCHP_DMA_C_DIS_HWFLC		(1UL << 19)
+#define MCHP_DMA_C_XFR_FLAGS_MASK0	0x0Ful
+#define MCHP_DMA_C_XFR_FLAGS_MASK	(0x0Ful << 16)
 #define MCHP_DMA_C_XFRU_POS		20u
 #define MCHP_DMA_C_XFRU_MASK0		0x07ul
 #define MCHP_DMA_C_XFRU_MASK		(0x07ul << 20)
@@ -386,7 +404,8 @@
 #define MCHP_DMA_STS_BUS_ERR		(1UL << 0)
 #define MCHP_DMA_STS_FLOW_CTRL_ERR	(1UL << 1)
 #define MCHP_DMA_STS_DONE		(1UL << 2)
-#define MCHP_DMA_STS_ALL		0x07ul
+#define MCHP_DMA_STS_DEV_TERM		(1UL << 3)
+#define MCHP_DMA_STS_ALL		0x0Ful
 
 /*
  * Channel Interrupt Enable, Offset 0x18
@@ -457,16 +476,6 @@
 #define MCHP_MAX_DMA_CHAN		12u
 #define MCHP_NUM_DMA_CHAN_NO_ALU	((MCHP_MAX_DMA_CHAN) - 2)
 
-/**
-  * @brief DMA Main (DMAM)
-  */
-typedef struct dma_main_regs
-{		/*!< (@ 0x40002400) DMA Structure */
-	__IOM uint8_t ACTRST;	/*!< (@ 0x00000000) DMA block activate/reset */
-	uint8_t RSVDA[3];
-	__IM uint32_t DATA_PKT;	/*!< (@ 0x00000004) DMA data packet (RO) */
-	__IM uint32_t ARB_FSM;	/*!< (@ 0x00000008) DMA Arbiter FSM (RO) */
-} DMAM_Type;
 
 /*
  * NOTE: structure size is 0x40 (64) bytes as each channel
@@ -477,6 +486,16 @@ typedef struct dma_main_regs
  * Channel 0 ALU is specialized for CRC-32 calculations.
  * Channel 1 ALU is specialized for memory fill.
  */
+/**
+  * @brief DMA Main (DMAM)
+  */
+typedef struct dma_main_regs
+{
+	__IOM uint8_t ACTRST;	/*!< (@ 0x0000) DMA block activate/reset */
+	uint8_t RSVDA[3];
+	__IM uint32_t DATA_PKT;	/*!< (@ 0x0004) DMA data packet (RO) */
+	__IM uint32_t ARB_FSM;	/*!< (@ 0x0008) DMA Arbiter FSM (RO) */
+} DMAM_Type;
 
 /**
   * @brief DMA Channels 0 and 1 with ALU
@@ -522,6 +541,20 @@ typedef struct dma_chan_regs
 	uint8_t RSVD4[0x20];	/* pad to 0x40(64) byte size */
 } DMA_CHAN_Type;
 
+/**
+  * @brief DMA (DMA) contains DMA Main and channels
+  */
+typedef struct dma_regs
+{
+	__IOM uint8_t ACTRST;	/*!< (@ 0x0000) DMA block activate/reset */
+	uint32_t RSVDA[1];
+	__IM uint32_t DATA_PKT;	/*!< (@ 0x0004) DMA data packet (RO) */
+	__IM uint32_t ARB_FSM;	/*!< (@ 0x0008) DMA Arbiter FSM (RO) */
+	uint32_t RSVDB[12];
+	DMA_CHAN_ALU_Type CHAN[MCHP_NUM_DMA_CHANNELS]; /*!< (@0x0040 - 0x033F) channels */
+} DMA_Type;
+
+
 #endif				// #ifndef _DMA_H
 /* end dma.h */
 /**	  @}

diff --git a/mec/mec1501/component/ecia.h b/mec/mec1501/component/ecia.h
@@ -41,6 +41,7 @@
 #define MCHP_ECIA_ADDR	0x4000E000ul
 #define MCHP_FIRST_GIRQ	8u
 #define MCHP_LAST_GIRQ	26u
+#define MCHP_NUM_GIRQS (MCHP_LAST_GIRQ - MCHP_FIRST_GIRQ + 1)
 
 #define MCHP_ECIA_GIRQ_NO_NVIC	 22u
 
@@ -54,6 +55,12 @@
 	(1ul << 19) + (1ul << 20) +\
 	(1ul << 21) + (1ul << 23))
 
+/*
+ * All external NVIC connections equal to or above this value are
+ * direct peripheral interrupts.
+ */
+#define MCHP_ECIA_FIRST_DIRECT_NVIC	20u
+
 /*
  * ARM Cortex-M4 NVIC registers
  * External sources are grouped by 32-bit registers.
@@ -383,6 +390,18 @@ typedef struct ecia_regs
 	__IM uint32_t BLK_ACTIVE;	/*! (@ 0x00000204) GIRQ Active bitmap (RO) */
 } ECIA_Type;
 
+/*
+ * ECIA registers with GIRQ accessible as an array
+ */
+typedef struct ecia_gar_regs
+{
+	GIRQ_Type GIRQ[MCHP_NUM_GIRQS]; /*!< (@ 0x0000-0x17B) GIRQ08-GIRQ26 */
+	uint8_t RSVD1[(0x0200ul - 0x017Cul)];	/* offsets 0x017C - 0x1FF */
+	__IOM uint32_t BLK_EN_SET;	/*! (@ 0x00000200) Aggregated GIRQ output Enable Set */
+	__IOM uint32_t BLK_EN_CLR;	/*! (@ 0x00000204) Aggregated GIRQ output Enable Clear */
+	__IM uint32_t BLK_ACTIVE;	/*! (@ 0x00000204) GIRQ Active bitmap (RO) */
+} ECIA_GAR_Type;
+
 #endif				// #ifndef _ECIA_H
 /* end ecia.h */
 /**   @}

diff --git a/mec/mec1501/component/espi_io.h b/mec/mec1501/component/espi_io.h
@@ -188,16 +188,16 @@
 	((0x01u) << (MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS))
 
 /* PC Ready */
-#define MCHP_ESPI_PC_READY_MASK		0x01u;
-#define MCHP_ESPI_PC_READY		0x01u;
+#define MCHP_ESPI_PC_READY_MASK		0x01u
+#define MCHP_ESPI_PC_READY		0x01u
 
 /* OOB Ready */
-#define MCHP_ESPI_OOB_READY_MASK	0x01u;
-#define MCHP_ESPI_OOB_READY		0x01u;
+#define MCHP_ESPI_OOB_READY_MASK	0x01u
+#define MCHP_ESPI_OOB_READY		0x01u
 
 /* FC Ready */
-#define MCHP_ESPI_FC_READY_MASK		0x01u;
-#define MCHP_ESPI_FC_READY		0x01u;
+#define MCHP_ESPI_FC_READY_MASK		0x01u
+#define MCHP_ESPI_FC_READY		0x01u
 
 /* ESPI_RESET# Interrupt Status */
 #define MCHP_ESPI_RST_ISTS_MASK		0x03u;