arm: exx32: Add Silabs EFM32PG12B soc files

The Silicon Labs EFM32 Pearl Gecko MCU includes: * Cortex-M4F core at 40MHz * up to 1024KB of flash and 256KB of RAM * multiple low power peripherals Ported from EFM32WG: https://www.silabs.com/documents/public/application-notes/an0918.0-efm32_to_efm32jgpg_migration_guide.pdf Signed-off-by: Gil Benkö <gil.benkoe@pm.me> Signed-off-by: Christian Taedcke <hacking@taedcke.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
zephyrproject-rtos · Nov 21, 2018 · 5fb053e · 5fb053e
1 parent 16ac7df
commit 5fb053e
Show file tree

Hide file tree

Showing 11 changed files with 553 additions and 0 deletions.
diff --git a/dts/arm/silabs/efm32pg12b.dtsi b/dts/arm/silabs/efm32pg12b.dtsi
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2018 Christian Taedcke <hacking@taedcke.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+	       device_type = "memory";
+	       compatible = "mmio-sram";
+	};
+
+	soc {
+		flash-controller@400e0000 {
+			compatible = "silabs,gecko-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x400e0000 0x104>;
+			interrupts = <25 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_0";
+				write-block-size = <4>;
+			};
+		};
+
+		usart0: usart@40010000 { /* USART0 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010000 0x400>;
+			interrupts = <12 0 13 0>;
+			interrupt-names = "rx", "tx";
+			status = "disabled";
+			label = "USART_0";
+		};
+
+		usart1: usart@40010400 { /* USART1 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010400 0x400>;
+			interrupts = <20 0 21 0>;
+			interrupt-names = "rx", "tx";
+			status = "disabled";
+			label = "USART_1";
+		};
+
+		usart2: usart@40010800 { /* USART2 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010800 0x400>;
+			interrupts = <40 0 41 0>;
+			interrupt-names = "rx", "tx";
+			status = "disabled";
+			label = "USART_2";
+		};
+
+		usart3: usart@40010c00 { /* USART3 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010c00 0x400>;
+			interrupts = <43 0 44 0>;
+			interrupt-names = "rx", "tx";
+			status = "disabled";
+			label = "USART_3";
+		};
+
+		leuart0: leuart@4004a000 { /* LEUART0 */
+			compatible = "silabs,gecko-leuart";
+			reg = <0x4004a000 0x400>;
+			interrupts = <22 0>;
+			status = "disabled";
+			label = "LEUART_0";
+		};
+
+		i2c0: i2c@4000c000 {
+			compatible = "silabs,gecko-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4000c000 0x400>;
+			interrupts = <17 0>;
+			label = "I2C_0";
+			status = "disabled";
+		};
+
+		i2c1: i2c@4000c400 {
+			compatible = "silabs,gecko-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4000c400 0x400>;
+			interrupts = <42 0>;
+			label = "I2C_1";
+			status = "disabled";
+		};
+
+		gpio@4000a400 {
+			compatible = "silabs,efm32-gpio";
+			reg = <0x4000a400 0xf00>;
+			interrupts = <1 2 11 2>;
+			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
+			label = "GPIO";
+
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@4000a000 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x4000a000 0x30>;
+				label = "GPIO_A";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiob: gpio@4000a030 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x4000a030 0x30>;
+				label = "GPIO_B";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpioc: gpio@4000a060 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x4000a060 0x30>;
+				label = "GPIO_C";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiod: gpio@4000a090 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x4000a090 0x30>;
+				label = "GPIO_D";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpioe: gpio@4000a0c0 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x4000a0c0 0x30>;
+				label = "GPIO_E";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiof: gpio@4000a0f0 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x4000a0f0 0x30>;
+				label = "GPIO_F";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/silabs/efm32pg12b500f1024gl125.dtsi b/dts/arm/silabs/efm32pg12b500f1024gl125.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/efm32pg12b.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(256)>;
+	};
+
+	soc {
+		flash-controller@400e0000 {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+
+};
diff --git a/soc/arm/silabs_exx32/Kconfig b/soc/arm/silabs_exx32/Kconfig
@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2017 Christian Taedcke
+# Copyright (c) 2018 Gil Benkoe
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -22,6 +23,7 @@ config SOC_PART_NUMBER
 	default SOC_PART_NUMBER_EXX32_EFR32FG1P if SOC_SERIES_EFR32FG1P
 	default SOC_PART_NUMBER_EXX32_EFM32HG if SOC_SERIES_EFM32HG
 	default SOC_PART_NUMBER_EXX32_EFR32MG12P if SOC_SERIES_EFR32MG12P
+	default SOC_PART_NUMBER_EXX32_EFM32PG12B if SOC_SERIES_EFM32PG12B
 	help
 	  This string holds the full part number of the SoC. It is a hidden option
 	  that you should not set directly. The part number selection choice defines

diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.efm32pg12b b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.efm32pg12b
@@ -0,0 +1,49 @@
+# Kconfig - Silicon Labs EFM32PG-STK3402A platform configuration options
+
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EFM32PG12B
+
+config SOC
+	string
+	default "efm32pg12b"
+
+config GPIO
+	default y
+
+if GPIO
+
+config GPIO_GECKO
+	default y
+
+endif # GPIO
+
+if SERIAL
+
+config UART_GECKO
+	default y
+
+config LEUART_GECKO
+	default y
+
+endif # SERIAL
+
+if I2C
+
+config I2C_GECKO
+	default y
+
+endif # I2C
+
+if FLASH
+
+config SOC_FLASH_GECKO
+	default y
+
+endif # FLASH
+
+endif # SOC_EFM32
diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series
@@ -0,0 +1,22 @@
+# Kconfig - EFM32PG12B series configuration options
+
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_EFM32PG12B
+
+config SOC_SERIES
+	default "efm32pg12b"
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 50
+
+source "soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.e*"
+
+endif # SOC_SERIES_EFM32PG12B
+
diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series
@@ -0,0 +1,17 @@
+# Kconfig - EFM32PG12B MCU line
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_EFM32PG12B
+	bool "EFM32PG12B Series MCU"
+	select HAS_SILABS_GECKO
+	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
+	select SOC_FAMILY_EXX32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select CPU_HAS_SYSTICK
+	help
+	  Enable support for EFM32 PearlGecko MCU series
diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc
@@ -0,0 +1,32 @@
+# Kconfig - EFM32PG12B MCU line
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "EFM32 Pearl Gecko MCU Selection"
+depends on SOC_SERIES_EFM32PG12B
+
+config SOC_EFM32PG12B
+	bool "SOC_EFM32PG12B"
+	select HAS_CMU
+	select HAS_EMU
+
+endchoice
+
+if SOC_SERIES_EFM32PG12B
+
+config SOC_PART_NUMBER_EFM32PG12B500F1024GL125
+	bool
+
+config SOC_PART_NUMBER_EXX32_EFM32PG12B
+	string
+	default "EFM32PG12B500F1024GL125" if SOC_PART_NUMBER_EFM32PG12B500F1024GL125
+	help
+	  This string holds the full part number of the SoC. It is a hidden option
+	  that you should not set directly. The part number selection choice defines
+	  the default value for this string.
+
+endif # SOC_SERIES_EFM32PG12B