boards: arm: fk7b0m1_vbt6: add support to external NOR Flash

Updates the DTS file by adding support for QSPI and SPI NOR Flash.

Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>

boards/arm/fk7b0m1_vbt6/doc/index.rst

@@ -57,14 +57,16 @@ More information about STM32H7B0VB can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_h723zg board configuration supports the following hardware
+The Zephyr fk7b0m1_vbt6 board configuration supports the following hardware
 features:
 
 +-------------+------------+-------------------------------------+
 | Interface   | Controller | Driver/Component                    |
 +=============+============+=====================================+
 | NVIC        | on-chip    | nested vector interrupt controller  |
 +-------------+------------+-------------------------------------+
+| FLASH       | on-chip    | flash memory                         |
++-------------+------------+-------------------------------------+
 | UART        | on-chip    | serial port                         |
 +-------------+------------+-------------------------------------+
 | PINMUX      | on-chip    | pinmux                              |
@@ -75,6 +77,10 @@ features:
 +-------------+------------+-------------------------------------+
 | Backup SRAM | on-chip    | Backup SRAM                         |
 +-------------+------------+-------------------------------------+
+| SPI         | on-chip    | spi bus                             |
++-------------+------------+-------------------------------------+
+| OCTOSPI     | on-chip    | octospi                             |
++-------------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
@@ -121,6 +127,24 @@ USB
 - USB D- = PA11
 - USB D+ = PA12
 
+SPI NOR Flash
+-------------
+
+- SPI1_MISO = PB4
+- SPI1_MOSI = PB5
+- SPI1_SCK = PB3
+- SPI1_CS = PA15
+
+OCTOSPI NOR Flash
+-----------------
+
+- OCTOSPI_CLK = PB2
+- OCTOSPI_NCS = PB6
+- OCTOSPI_IO0 = PD11
+- OCTOSPI_IO1 = PD12
+- OCTOSPI_IO2 = PE2
+- OCTOSPI_IO3 = PD13
+
 System Clock
 ============
 

boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.dts

@@ -41,6 +41,7 @@
 	aliases {
 		led0 = &user_led;
 		sw0 = &user_button;
+		spi-flash0 = &w25q64jvssiq_spi;
 	};
 };
 
@@ -75,6 +76,61 @@
 	d3ppre = <2>;
 };
 
+&octospi1 {
+	pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pb6
+		     &octospim_p1_io0_pd11 &octospim_p1_io1_pd12
+		     &octospim_p1_io2_pe2 &octospim_p1_io3_pd13>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	/* Winbond external flash */
+	w25q64jvssiq_qspi: qspi-nor-flash@0 {
+		compatible = "st,stm32-ospi-nor";
+		reg = <0>;
+		ospi-max-frequency = <DT_FREQ_M(133)>;
+		size = <(DT_SIZE_M(8) * 8)>; /* 64 Mbits = 8 MBytes */
+		spi-bus-width = <OSPI_QUAD_MODE>;
+		data-rate = <OSPI_STR_TRANSFER>;
+		writeoc = "PP_1_1_4";
+		status = "okay";
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			slot0_partition: partition@0 {
+				reg = <0x00000000 DT_SIZE_M(64)>;
+			};
+		};
+	};
+};
+
+&spi6 {
+	pinctrl-0 = <&spi6_sck_pb3 &spi6_miso_pb4 &spi6_mosi_pb5>;
+	cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	status = "okay";
+	w25q64jvssiq_spi: spi-nor-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+		size = <(DT_SIZE_M(8) * 8)>; /* 64 Mbits = 8 MBytes */
+		status = "okay";
+		jedec-id = [ef 40 17];
+		has-dpd;
+		t-enter-dpd = <3500>;
+		t-exit-dpd = <3500>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			storage_partition: partition@0 {
+				label = "storage";
+				reg = <0x00000000 DT_SIZE_M(64)>;
+			};
+		};
+	};
+};
+
 &usart1 {
 	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
 	pinctrl-names = "default";