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ARM: Introduce Infineon PSoC 6 SoC #44211

Merged
merged 12 commits into from
Mar 1, 2023
Merged

ARM: Introduce Infineon PSoC 6 SoC #44211

merged 12 commits into from
Mar 1, 2023

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npal-cy
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@npal-cy npal-cy commented Mar 25, 2022 •
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This introduce an Infineon PSoC 6 SoC (#42883).
This is a first MR which include following part:

The next PRs will include Counter driver, CYW42XXX BT HCI extension driver, CYW42XXX wifi driver, etc.

PSoC 6 Integration structure:
image

This PR has addressed comments from previous draft: #42725

To decrease number of files for review the tds and soc has files only for one MPN (CY8C624ABZI_S2D44), and die family (psoc6_02):

Rest of MPNs, die families will be added in separate PR .

@github-actions github-actions bot added area: API Changes to public APIs area: Devicetree area: Devicetree Binding PR modifies or adds a Device Tree binding labels Mar 25, 2022
@npal-cy npal-cy mentioned this pull request Mar 25, 2022
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npal-cy commented Mar 30, 2022

hi All,
I am working on fixing https://github.com/zephyrproject-rtos/zephyr/runs/5692202883?check_suite_focus=true
i see many checks-warn related to device tree dts/arm/infineon/psoc6, but when i run check_compliance on my side (Ubuntu), i do not see any device tree warnings.
./scripts/ci/check_compliance.py -m Codeowners -m Devicetree -m Gitlint -m Identity -m Nits -m pylint -m checkpatch -m Kconfig

investigating this. Maybe someone has ideas why a have different results in check_compliance.

@npal-cy npal-cy force-pushed the topic/infineon_cat1_integration_github branch 2 times, most recently from b0ae948 to 234c41b Compare April 16, 2022 21:11
@npal-cy npal-cy closed this Apr 16, 2022
@npal-cy npal-cy reopened this Apr 16, 2022
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npal-cy commented Apr 16, 2022

Now compliance checks is clear. We have one warning, which is expected:

197cce89cd4a6ea3740ddc37f0edb00c0747702b:158: WARNING:NEW_TYPEDEFS: do not add new typedefs
#158: FILE: soc/arm/infineon_cat1/common/pinctrl_soc.h:48:
+typedef struct {

pinctrl requires to have typedef for pinctrl_soc_pin_t

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npal-cy commented Apr 17, 2022

Added clock control driver and Infineon CY8CPROTO-062-4343W board. This is all content for this PR.

@npal-cy npal-cy force-pushed the topic/infineon_cat1_integration_github branch 4 times, most recently from 286b43e to 8e7c66a Compare April 18, 2022 09:29
@npal-cy npal-cy marked this pull request as ready for review April 18, 2022 19:50
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@nandojve @gmarull @MaureenHelm @henrikbrixandersen reviews appreciated.

@npal-cy npal-cy dismissed stale reviews from ifyall and yurii2001lozyn via a654b46 February 24, 2023 22:23
@npal-cy npal-cy force-pushed the topic/infineon_cat1_integration_github branch from 5197387 to a654b46 Compare February 24, 2023 22:23
@npal-cy npal-cy force-pushed the topic/infineon_cat1_integration_github branch from a654b46 to 4b0726d Compare February 26, 2023 20:35
mniestroj
mniestroj previously approved these changes Feb 27, 2023
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gmarull
gmarull previously approved these changes Feb 28, 2023
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I think major issues have been addressed, should be good to go

@npal-cy
CODEOWNERS: Update codeowners for Infineon/Cypress sources
4f4ba6f 
- Add Ian Fyall (@ifyall) as codeowner for Infineon/Cypress sources.
- Add Nazar Palamar (@npal-cy) as codeowner for Infineon/Cypress sources.
- Remove Gerson Fernando Budke (@nandojve) from codeowner
of Cypress sources.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
MAINTAINERS.yml: Update maintainers for Cypress sources
14b5521 
- Remove Gerson Fernando Budke (@nandojve) from maintainers
of Cypress sources.

- Add Nazar Palamar (@npal-cy) as collaborators for
Infineon/Cypress sources.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
west.yml: Update hal_infineon revision
34a4a67 
Get blob support for cm0+ in hal_infineon

Updated revision of hal_infineon to:
8485083ad91d3e2cc5d706da3464716718a6a42e

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
modules: hal_infineon: Added mtb-hal-cat1 asset for Infenion Cat1 dev…
1a9eb98 
…ices

- Add Cmakefiles for mtb-hal-cat1
- Update top makefile

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
modules: hal_infineon: Added blob support for CM0+ images
e451ce8 
Initial blob support for PSoC6 CM0+ images

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
dts: arm: Introduce Infineon PSoC 6 SOC Devicetree
cc848c2 
Added initial version of Devicetree for Infineon PSoC 6 SOC with following
structure:
 1. MPN devicetree files
  |--> psoc6
    |--> mpns
         |--> CY8C6016BZI_F04.dtsi
         |--> CY8C6036BZI_F04.dtsi
         |--> CY****.dtsi

  Those file describes cpus, flash-controller, sram memory, nvic option. It
  includes the package dtsi (e.g. psoc6_02.124-bga.dtsi) with information
  about gpio (based on package e.g. 68-qfn, 128-tqfp, 124-bga, etc.) and
  peripherals for (based on PSoC 6 series, psoc6_01, psoc6_02, etc).

  MPN devicetree file is main platform dtsi file, which should be included
  from board dts (e.g cy8cproto_062_4343w.dts), example:
  #include <infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi>

 2. Devicetree files for PSoC 6 series 02 (2M).
  Includes: psoc6_02.dtsi - peripherals dtsi psoc6_01.xxxxx.dtsi - package
  dtsi. User does not directly include those files.
  It automatically includes via MPN dtsi.
   |--> psoc6_02
         |--> psoc6_02.dtsi
         |--> psoc6_02.100-wlcsp.dtsi
         |--> psoc6_02.124-bga.dtsi
         |--> psoc6_02.128-tqfp.dtsi
         |--> psoc6_02.68-qfn.dtsi

  In future PR/commits will be added Devicetree for support all
  PSoC 6 series:
   - for PSoC 6 series 01 (1M)
   - for PSoC 6 series 03 (512)
   - for PSoC 6 series 04 (256)

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@galak galak dismissed their stale review February 28, 2023 17:54

issues look like they are addressed

@npal-cy
soc: arm: Introduce Infineon CAT1/PSoC 6 SOC integration
fca19c1 
Add initial version of Infineon CAT1/PSoC 6 SOC integration.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
drivers: pinctrl: Add Infineon CAT1 Pin controller driver
673054c 
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
drivers: clock_control: Add Infineon CAT1 clock control driver
7242553 
Add initial version of Infineon CAT1 clock control driver.
- supports clock initialization based on board DT configuration.

Added initial version of system_clocks.dtsi for Infineon PSoC 6 SOC.
Includes: clk_imo, path_mux0..4, fll0, pll0, clk_hf0..4, clk_fast,
clk_slow and clk_peri.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
drivers: serial: Add Infineon CAT1 UART driver
ee720c2 
Added initial version of Infineon CAT1 UART driver.
Added initial version of binding file for Infineon CAT1 UART driver.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
drivers: gpio: Add Infineon CAT1 GPIO driver
13742fd 
Added initial version of Infineon CAT1 GPIO driver.
Added initial version of binding file for Infineon CAT1 GPIO driver.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy
boards: arm: Introduce Infineon CY8CPROTO-062-4343W board
e1e57eb 
Add initial version of CY8CPROTO-062-4343W board.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
@npal-cy npal-cy dismissed stale reviews from gmarull and mniestroj via e1e57eb February 28, 2023 22:41
@npal-cy npal-cy force-pushed the topic/infineon_cat1_integration_github branch from 4b0726d to e1e57eb Compare February 28, 2023 22:41
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npal-cy commented Feb 28, 2023

Updated RAM/ROM size implementation for CM0p images.

PSOC6/CAT1 stop works after commit 44628735, where was updated rom_start_offset(add to address instead of set.)

The following updates was done to handled 44628735 changes:

  • added own hidden SOC_PSOC6_CM0P_IMAGE_ROM/RAM_SIZE kconfig object to handle RAM/ROM size for PSOC6 CM0P images.
  • replaced ROM_START_OFFSET to SOC_PSOC6_CM0P_IMAGE_ROM_SIZE in soc/arm/infineon_cat1/psoc6/Kconfig.defconfig
  • replaced SRAM_OFFSET to SOC_PSOC6_CM0_IMAGE_RAM_SIZE in soc/arm/infineon_cat1/psoc6/Kconfig.defconfig
  • updated soc/arm/infineon_cat1/psoc6/rom_cm0image.ld and /soc/arm/infineon_cat1/psoc6/ram_cm0image.ld to use CONFIG_SOC_PSOC6_CM0P_IMAGE_ROM/RAM_SIZE

rebased commit: fca19c1

carlescufi
carlescufi approved these changes Mar 1, 2023
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The manifest and binary blobs changes LGTM.

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The Compliance Failures are just the usual pinctrl typedef.

@carlescufi carlescufi merged commit 41eec53 into zephyrproject-rtos:main Mar 1, 2023
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area: API Changes to public APIs area: Boards area: Clock Control area: Devicetree Binding PR modifies or adds a Device Tree binding area: Devicetree area: Documentation area: GPIO area: Pinctrl area: Process area: UART Universal Asynchronous Receiver-Transmitter manifest manifest-hal_infineon TSC Topics that need TSC discussion
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