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RFC: arch: arm: Remove aarch32 directory and split Cortex-M and Cortex-A/r code #60031

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12 changes: 6 additions & 6 deletions CODEOWNERS
Validating CODEOWNERS rules …
Original file line number Diff line number Diff line change
Expand Up @@ -18,9 +18,9 @@
/MAINTAINERS.yml @MaureenHelm
/arch/arc/ @abrodkin @ruuddw @evgeniy-paltsev
/arch/arm/ @MaureenHelm @galak @ioannisg
/arch/arm/core/aarch32/cortex_m/cmse/ @ioannisg
/arch/arm/include/aarch32/cortex_m/cmse.h @ioannisg
/arch/arm/core/aarch32/cortex_a_r/ @MaureenHelm @galak @ioannisg @bbolen @stephanosio
/arch/arm/core/cortex_m/cmse/ @ioannisg
/arch/arm/include/cortex_m/cmse.h @ioannisg
Comment on lines +21 to +22
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This should probably be updated to @SgrrZhf @povergoing @microbuilder Since Ioannis is no longer involved with the project.

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Sorry, ignore this and lets make a separate PR since there are a lot of instances of this, and I agree with @carlocaione ... lets separate M and A/R here, and nothing else. I'll make a PR to cleanup CODEOWNERS later.

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Updating the CODEOWNERS might also be a chance to officially blame me for the MMU stuff for everyone to see...

/arch/arm/core/cortex_a_r/ @MaureenHelm @galak @ioannisg @bbolen @stephanosio
/arch/arm64/ @carlocaione
/arch/arm64/core/cortex_r/ @povergoing
/arch/arm64/core/xen/ @lorc @firscity
Expand Down Expand Up @@ -655,11 +655,11 @@
/include/zephyr/arch/arc/ @abrodkin @ruuddw @evgeniy-paltsev
/include/zephyr/arch/arc/arch.h @abrodkin @ruuddw @evgeniy-paltsev
/include/zephyr/arch/arc/v2/irq.h @abrodkin @ruuddw @evgeniy-paltsev
/include/zephyr/arch/arm/aarch32/ @MaureenHelm @galak @ioannisg
/include/zephyr/arch/arm/aarch32/cortex_a_r/ @stephanosio
/include/zephyr/arch/arm @MaureenHelm @galak @ioannisg
/include/zephyr/arch/arm/cortex_a_r/ @stephanosio
/include/zephyr/arch/arm64/ @carlocaione
/include/zephyr/arch/arm64/cortex_r/ @povergoing
/include/zephyr/arch/arm/aarch32/irq.h @carlocaione
/include/zephyr/arch/arm/irq.h @carlocaione
/include/zephyr/arch/mips/ @frantony
/include/zephyr/arch/nios2/ @nashif
/include/zephyr/arch/nios2/arch.h @nashif
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1 change: 0 additions & 1 deletion MAINTAINERS.yml
Original file line number Diff line number Diff line change
Expand Up @@ -141,7 +141,6 @@ ARM arch:
files:
- arch/arm/
- arch/arm/core/offsets/
- include/zephyr/arch/arm/aarch32/
- include/zephyr/arch/arm/
- tests/arch/arm/
- doc/hardware/arch/arm_cortex_m.rst
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/CMakeLists.txt
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Expand Up @@ -2,4 +2,4 @@

set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm)

add_subdirectory(core/aarch32)
add_subdirectory(core)
4 changes: 2 additions & 2 deletions arch/arm/Kconfig
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Expand Up @@ -69,7 +69,7 @@ config ARM_ON_EXIT_CPU_IDLE
observed on some SoCs caused by a memory access following WFI/WFE
instructions.

rsource "core/aarch32/Kconfig"
rsource "core/aarch32/Kconfig.vfp"
rsource "core/Kconfig"
rsource "core/Kconfig.vfp"

endmenu
Original file line number Diff line number Diff line change
Expand Up @@ -3,22 +3,14 @@
zephyr_library()

zephyr_library_sources(
cpu_idle.S
fatal.c
irq_manage.c
nmi.c
nmi_on_reset.S
prep_c.c
swap.c
swap_helper.S
thread.c
)

zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
zephyr_library_sources_ifdef(CONFIG_CPP __aeabi_atexit.c)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
zephyr_library_sources_ifdef(CONFIG_ARM_ZIMAGE_HEADER header.S)

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19 changes: 0 additions & 19 deletions arch/arm/core/aarch32/cortex_a_r/thread.c

This file was deleted.

17 changes: 0 additions & 17 deletions arch/arm/core/aarch32/cortex_m/thread.c

This file was deleted.

Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,15 @@ zephyr_library_sources(
stacks.c
tcm.c
vector_table.S
swap.c
swap_helper.S
irq_manage.c
prep_c.c
thread.c
cpu_idle.S
)

zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c)
zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S)
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95 changes: 95 additions & 0 deletions arch/arm/core/cortex_a_r/cpu_idle.S
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@@ -0,0 +1,95 @@
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* @file
* @brief ARM Cortex-A and Cortex-R power management
*
*/

#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>

#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
#include <soc_cpu_idle.h>
#endif

_ASM_FILE_PROLOGUE

GTEXT(arch_cpu_idle)
GTEXT(arch_cpu_atomic_idle)

.macro _sleep_if_allowed wait_instruction
#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
push {r0, lr}
bl z_arm_on_enter_cpu_idle
/* Skip the wait instruction if on_enter_cpu_idle() returns false. */
cmp r0, #0
beq _skip_\@
#endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */

/*
* Wait for all memory transactions to complete before entering low
* power state.
*/
dsb
\wait_instruction

#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
/* Inline the macro provided by SoC-specific code */
SOC_ON_EXIT_CPU_IDLE
#endif /* CONFIG_ARM_ON_EXIT_CPU_IDLE */

#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
_skip_\@:
pop {r0, lr}
#endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */
.endm

SECTION_FUNC(TEXT, arch_cpu_idle)
#ifdef CONFIG_TRACING
push {r0, lr}
bl sys_trace_idle
pop {r0, lr}
#endif /* CONFIG_TRACING */

/* Enter low power state */
_sleep_if_allowed wfi

/*
* Clear PRIMASK and flush instruction buffer to immediately service
* the wake-up interrupt.
*/
cpsie i
isb

bx lr

SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
#ifdef CONFIG_TRACING
push {r0, lr}
bl sys_trace_idle
pop {r0, lr}
#endif /* CONFIG_TRACING */

/*
* Lock PRIMASK while sleeping: wfe will still get interrupted by
* incoming interrupts but the CPU will not service them right away.
*/
cpsid i

/* r0: interrupt mask from caller */

/* No BASEPRI, call wfe directly
*/
_sleep_if_allowed wfe

cmp r0, #0
bne _irq_disabled
cpsie i
_irq_disabled:

bx lr
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ _ASM_FILE_PROLOGUE

GTEXT(z_arm_exc_exit)
GTEXT(z_arm_int_exit)
GTEXT(z_arm_pendsv)
GTEXT(z_arm_do_swap)
GDATA(_kernel)

.macro userspace_exc_exit
Expand Down Expand Up @@ -148,7 +148,7 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit)
ldr r1, [r3, #_kernel_offset_to_current]
ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
cmp r0, r1
blne z_arm_pendsv
blne z_arm_do_swap
__EXIT_INT:
#endif /* CONFIG_PREEMPT_ENABLED */

Expand Down Expand Up @@ -231,12 +231,12 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)
/*
* Switch in the next scheduled thread.
*
* Note that z_arm_pendsv must be called in the SVC mode because it
* Note that z_arm_do_swap must be called in the SVC mode because it
* switches to the SVC mode during context switch and returns to the
* caller using lr_svc.
*/
cps #MODE_SVC
bl z_arm_pendsv
bl z_arm_do_swap

/* Decrement exception nesting count */
ldr r3, =_kernel
Expand Down
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