Merge pull request #19031 from antlilja/llvm-bc

Emit LLVM bitcode without using LLVM
ziglang · Feb 24, 2024 · b344ff0 · b344ff0
2 parents 8d651f5 + edb6486
commit b344ff0
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Showing 10 changed files with 8,605 additions and 5,425 deletions.
diff --git a/lib/std/meta.zig b/lib/std/meta.zig
@@ -460,13 +460,12 @@ test "std.meta.FieldType" {
     try testing.expect(FieldType(U, .d) == *const u8);
 }
 
-pub fn fieldNames(comptime T: type) *const [fields(T).len][]const u8 {
+pub fn fieldNames(comptime T: type) *const [fields(T).len][:0]const u8 {
     return comptime blk: {
         const fieldInfos = fields(T);
-        var names: [fieldInfos.len][]const u8 = undefined;
-        for (fieldInfos, 0..) |field, i| {
-            names[i] = field.name;
-        }
+        var names: [fieldInfos.len][:0]const u8 = undefined;
+        // This concat can be removed with the next zig1 update.
+        for (&names, fieldInfos) |*name, field| name.* = field.name ++ "";
         break :blk &names;
     };
 }

diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
@@ -16683,36 +16683,44 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
                             else => null,
                         };
                         defer if (elem_lock) |lock| self.register_manager.unlockReg(lock);
-                        const elem_reg = registerAlias(
-                            try self.copyToTmpRegister(elem_ty, mat_elem_mcv),
-                            elem_abi_size,
-                        );
+
                         const elem_extra_bits = self.regExtraBits(elem_ty);
-                        if (elem_bit_off < elem_extra_bits) {
-                            try self.truncateRegister(elem_ty, elem_reg);
+                        {
+                            const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv);
+                            const temp_alias = registerAlias(temp_reg, elem_abi_size);
+                            const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg);
+                            defer self.register_manager.unlockReg(temp_lock);
+
+                            if (elem_bit_off < elem_extra_bits) {
+                                try self.truncateRegister(elem_ty, temp_alias);
+                            }
+                            if (elem_bit_off > 0) try self.genShiftBinOpMir(
+                                .{ ._l, .sh },
+                                elem_ty,
+                                .{ .register = temp_alias },
+                                Type.u8,
+                                .{ .immediate = elem_bit_off },
+                            );
+                            try self.genBinOpMir(
+                                .{ ._, .@"or" },
+                                elem_ty,
+                                .{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } },
+                                .{ .register = temp_alias },
+                            );
                         }
-                        if (elem_bit_off > 0) try self.genShiftBinOpMir(
-                            .{ ._l, .sh },
-                            elem_ty,
-                            .{ .register = elem_reg },
-                            Type.u8,
-                            .{ .immediate = elem_bit_off },
-                        );
-                        try self.genBinOpMir(
-                            .{ ._, .@"or" },
-                            elem_ty,
-                            .{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } },
-                            .{ .register = elem_reg },
-                        );
                         if (elem_bit_off > elem_extra_bits) {
-                            const reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv);
+                            const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv);
+                            const temp_alias = registerAlias(temp_reg, elem_abi_size);
+                            const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg);
+                            defer self.register_manager.unlockReg(temp_lock);
+
                             if (elem_extra_bits > 0) {
-                                try self.truncateRegister(elem_ty, registerAlias(reg, elem_abi_size));
+                                try self.truncateRegister(elem_ty, temp_alias);
                             }
                             try self.genShiftBinOpMir(
                                 .{ ._r, .sh },
                                 elem_ty,
-                                .{ .register = reg },
+                                .{ .register = temp_reg },
                                 Type.u8,
                                 .{ .immediate = elem_abi_bits - elem_bit_off },
                             );
@@ -16723,7 +16731,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
                                     .index = frame_index,
                                     .off = elem_byte_off + @as(i32, @intCast(elem_abi_size)),
                                 } },
-                                .{ .register = reg },
+                                .{ .register = temp_alias },
                             );
                         }
                     }