AMF-Placer 2.0: An Open-Source Timing-driven Analytical Mixed-size FPGA Placer

What's Changed

1. a set of timing optimization algorithms without involving static timing analysis (STA), e.g., path-length-aware SA-based floorplanning and parallelized CLB packing with timing factors considered.
2. an efficient piecewise regression model of pin-to-pin delay, utilized by our integrated lightweight parallelized timing analysis engine.
3. a placement-blockage-aware optimization scheme, which identifies the potential negative interference of placement blockage with long paths, spreads the instances in specific regions, and inserts placement anchors for the instances in the target paths to reduce cross-blockage routing.
4. a WNS-aware timing-driven global placement, based on quadratic programming and proper exploitation of pseudo-nets with slack-guided weights, which realizes the multi-objective optimization of WNS, TNS, and wirelength.
5. a sector-guided detailed placement algorithm, which can efficiently identify the instance movement with promising timing benefits. The timing can be comprehensively optimized by AMF-Placer~{2.0} at various granularity levels (i.e., multi-path, per-path, and per-instance).
6. A GUI for visualization of the placement procedure (zoom in / zoom out / critical path identification ...)

Clock+Level-Based-TimingOpt

What's Changed

1. Added level based net weight to reduce the net delay of long data paths
2. Added constraints to force long paths to locate in one column of clock regions for timing optimization and legalization
3. Tested user-defined cluster for different domains of designs
4. Fixed bugs related to specific cell types and parameter settings
5. More detailed documentations

New Contributors

• @magic3007 made their first contribution in #2

Full Changelog: ICCAD-2021...Clock+Level-Based-TimingOpt

AMF-Placer 0.1

Features

1. supports placement with a large number of mixed-size macros with shape constraints in practical FPGA applications.
2. a set of optional optimization techniques to improve mixed-size FPGA placement QoR
3. parallelize the implementation of each stage of placement based on multi-threading
4. modularized function implementation for easier further development
5. flexible and extensible JSON-based placement configuration
6. a set of pre-implementation benchmarks from the latest practical FPGA applications

Todo List

1. stable clock legalization
2. basic static timing analysis (doing)
3. timing term in analytical model (doing)
4. timing-driven detailed placement
5. More and more documentation...