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riscv-3-stage-pipelined-processor-core
riscv-3-stage-pipelined-processor-core PublicFully implemented 3 staged pipelined RISC-V processor with hazard detection unit. Hazard detection unit solves the hazards by stalling and forwarding technique. CSR and MRET Instructions are also s…
SystemVerilog 1
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duty-cycle-and-frequency-controlled-signal-using-verilog
duty-cycle-and-frequency-controlled-signal-using-verilog PublicWe will make a signal in Verilog which will be a variable duty cycle as well as variable frequency signal which is named as pulse. We can refer this signal pulse as a square wave also with variable…
Verilog 1
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spi-protocol
spi-protocol PublicSPI protocol is implemented and simulated successfully in this repository.
Verilog
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uart-application-in-real-time-simulation-emulation-on-fpga
uart-application-in-real-time-simulation-emulation-on-fpga PublicIf we run out of input pins on FPGA, we can instantiate receiver of uart in DUT (design under test). Receiver will receive data from PC serially and convert this serial data to parallel data and gi…
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