Duty cycle and Frequency Controlled Signal using Verilog

We will make a signal in Verilog which will be a variable duty cycle as well as variable frequency signal which is named as pulse. We can refer this signal pulse as a square wave also with variable duty cycle.

The picture of the simulation (The signal to be observed is named as pulse) is shown below:

Also, the video of the simulation is presented as:

video_of_simulation_of_square_wave.mp4