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1. OpenExSys_NoC OpenExSys_NoC Public

   OpenExSys_NoC a mesh-based network on chip IP.

   SystemVerilog 4

2. OpenExSys_CoherentCache OpenExSys_CoherentCache Public

   OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.

   SystemVerilog 2

3. ORV32s ORV32s Public

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4. axi_llc axi_llc Public

   Forked from pulp-platform/axi_llc

   SystemVerilog

5. axi axi Public

   Forked from pulp-platform/axi

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog

6. culsans culsans Public

   Forked from pulp-platform/culsans

   Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

   C