In this new era of high-performance computing, hardware accelerators play a pivotal role in handling a specific task or closely related set of tasks, offering significant performance improvements for those specific functions or operations. Some of these hardware accelerators are integrated into the central processing unit (CPU) itself. Hardware accelerators are meticulously crafted to deliver superior performance, and they often outperform general-purpose CPUs in their designated tasks. Ordinary Differential Equations (ODEs) play a fundamental role in modeling and simulating various dynamical systems. They provide an exact and analytical way to find exact solutions, but sometimes, it may be hard to obtain an accurate solution due to the complexity of the system. Here, numerical method analysis comes into play. These analyses help us in approximating the solutions to the differential equations, which makes it possible to study the behavior of the system effectively. The goal of this repository is to implement hardware accelerator design for Euler and Modified Euler methods of numerical analysis in solving ordinary differential equations. The latency of the IPs taken here for this repo is 0. For different IP latency specifications of the IP units, please refer to my other repos. The work has been specifically done using Very High-Speed Integrated Circuit Hardware Descriptive Language (VHDL) in Xilinx Vivado Software. The accelerator is typically deployed on the Zynq ZC702 FPGA Evaluation Kit.
The documentation for downloading Xilinx Vivado and the basic tutorial for learning VHDL has been given below:
Xilinx Vivado: [https://docs.xilinx.com/r/2022.1-English/ug973-vivado-release-notes-install-license/Download-and-Installation]
VHDL Tutorial: [https://www.eecs.umich.edu/courses/doing_dsp/handout/vhdl-tutorial.pdf]
Let's Start!