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Merge pull request #401 from liuhy-2020/chibios-21.11.x
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[MCU FS026]update library,hal,demo.
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@fpoussin
fpoussin committed Jun 1, 2024
2 parents e7dd416 + 24203f9 commit 052a4a2
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Showing 14 changed files with 580 additions and 204 deletions.
128 changes: 89 additions & 39 deletions demos/ES32/FS026/cfg/mcuconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,8 @@
#ifndef MCUCONF_H
#define MCUCONF_H

#define ES32_FS026_MCUCONF

/**
* @name Internal clock sources
* @{
Expand All @@ -28,22 +30,64 @@
/*
* HAL driver system settings.
*/
#define ES32_NO_INIT FALSE
#define ES32_MHSI_ENABLED TRUE
#define ES32_FHSI_ENABLED FALSE
#define ES32_LSI_ENABLED FALSE
#define ES32_HSE_ENABLED TRUE
#define ES32_LSE_ENABLED FALSE
#define ES32_PLL_ENABLED TRUE
#define ES32_MAINCLKSRC ES32_MAINCLKSRC_PLL
#define ES32_HSE_STATE ANCTL_HSECR0_HSEON
#define ES32_PLLSRC ES32_PLLSRC_HSE
#define ES32_PLLDIV_VALUE 2
#define ES32_PLLMUL_VALUE 12 // The allowed range is 12,16,20,24.
#define ES32_HPRE 1
#define ES32_PPRE1 1
#define ES32_PPRE2 1
#define ES32_USBPRE ES32_USBPRE_DIV1P5
#define ES32_NO_INIT FALSE

/*system_clk select
MD_RCU_SW_SYSCLK_HRC = HRC selected as system clock
MD_RCU_SW_SYSCLK_HOSC = HOSC selected as system clock
MD_RCU_SW_SYSCLK_PLL0 = PLL0 selected as system clock
MD_RCU_SW_SYSCLK_HRC48 = HRC48 selected as system clock
*/
#define ES32_SYSCLK_SOURSE_SELECT MD_RCU_SW_SYSCLK_PLL0

/*external clk config*/
#define ES32_HOSC_CLK_EN FALSE
#define ES32_HOSC_CLK_FREQ 8

/*pll clk config
MD_RCU_PLLSRC_HRC = HRC selected as PLL reference clock
MD_RCU_PLLSRC_HOSC = HOSC selected as PLL reference clock
MD_RCU_PLLSRC_HRC48 = HRC48 selected as PLL reference clock
MD_RCU_PLLCLK_PASS = 0
MD_RCU_PLLCLK_4M = 4000000
MD_RCU_PLLCLK_8M = 8000000
MD_RCU_PLLCLK_12M = 12000000
MD_RCU_PLLCLK_16M = 16000000
MD_RCU_PLLCLK_24M = 24000000
MD_RCU_PLLCLK_32M = 32000000
MD_RCU_PLLCLK_36M = 36000000
MD_RCU_PLLCLK_40M = 40000000
MD_RCU_PLLCLK_48M = 48000000
MD_RCU_PLLCLK_64M = 64000000
MD_RCU_PLLCLK_72M = 72000000
*/
#define ES32_PLL_CLK_EN TRUE
#define ES32_PLL_SOURSE_SELECT MD_RCU_PLLSRC_HRC48
#define ES32_PLL_CLK_FREQ MD_RCU_PLLCLK_72M

/*bus clk config
MD_RCU_HPRE_SYSCLK_DIV_1 = SYSCLK not divided
MD_RCU_HPRE_SYSCLK_DIV_2 = SYSCLK divided by 2
MD_RCU_HPRE_SYSCLK_DIV_4 = SYSCLK divided by 4
MD_RCU_HPRE_SYSCLK_DIV_8 = SYSCLK divided by 8
MD_RCU_HPRE_SYSCLK_DIV_16 = SYSCLK divided by 16
MD_RCU_HPRE_SYSCLK_DIV_64 = SYSCLK divided by 64
MD_RCU_HPRE_SYSCLK_DIV_128 = SYSCLK divided by 128
MD_RCU_HPRE_SYSCLK_DIV_256 = SYSCLK divided by 256
MD_RCU_HPRE_SYSCLK_DIV_512 = @brief SYSCLK divided by 512
MD_RCU_PPRE_HCLK_DIV_1 = HCLK not divided
MD_RCU_PPRE_HCLK_DIV_2 = HCLK divided by 2
MD_RCU_PPRE_HCLK_DIV_4 = HCLK divided by 4
MD_RCU_PPRE_HCLK_DIV_8 = HCLK divided by 8
MD_RCU_PPRE_HCLK_DIV_16 = HCLK divided by 16
*/
#define ES32_BUS_DIV_HPRE MD_RCU_HPRE_SYSCLK_DIV_1
#define ES32_BUS_DIV_PPRE MD_RCU_PPRE_HCLK_DIV_1

/*
* EXTI driver system settings.
Expand Down Expand Up @@ -88,15 +132,24 @@
/*
* PWM driver system settings.
*/
#define ES32_PWM_USE_ADVANCED FALSE
#define ES32_PWM_USE_TIM1 FALSE
#define ES32_PWM_USE_TIM2 FALSE
#define ES32_PWM_USE_TIM3 FALSE
#define ES32_PWM_USE_TIM4 FALSE
#define ES32_PWM_TIM1_IRQ_PRIORITY 7
#define ES32_PWM_TIM2_IRQ_PRIORITY 7
#define ES32_PWM_TIM3_IRQ_PRIORITY 7
#define ES32_PWM_TIM4_IRQ_PRIORITY 7
#define ES32_PWM_USE_AD16C4T1 TRUE
#define ES32_PWM_USE_GP32C4T1 TRUE
#define ES32_PWM_USE_GP16C4T1 TRUE
#define ES32_PWM_USE_GP16C4T2 TRUE
#define ES32_PWM_USE_GP16C4T3 TRUE
#define ES32_PWM_USE_GP16C2T1 TRUE
#define ES32_PWM_USE_GP16C2T2 TRUE
#define ES32_PWM_USE_GP16C2T3 TRUE
#define ES32_PWM_USE_GP16C2T4 TRUE
#define ES32_PWM_AD16C4T1_IRQ_PRIORITY 7
#define ES32_PWM_GP32C4T1_IRQ_PRIORITY 7
#define ES32_PWM_GP16C4T1_IRQ_PRIORITY 7
#define ES32_PWM_GP16C4T2_IRQ_PRIORITY 7
#define ES32_PWM_GP16C4T3_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T1_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T2_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T3_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T4_IRQ_PRIORITY 7

/*
* I2C driver system settings.
Expand All @@ -110,24 +163,20 @@
/*
* SERIAL driver system settings.
*/
#define ES32_SERIAL_USE_UART1 FALSE
#define ES32_SERIAL_USE_UART2 FALSE
#define ES32_SERIAL_USE_UART3 FALSE
#define ES32_SERIAL_USART1_PRIORITY 12
#define ES32_SERIAL_USART2_PRIORITY 12
#define ES32_SERIAL_USART3_PRIORITY 12
#define ES32_SERIAL_USE_UART1 TRUE
#define ES32_SERIAL_USE_UART2 TRUE
#define ES32_SERIAL_USE_UART3 TRUE
#define ES32_SERIAL_USE_UART4 TRUE
#define ES32_SERIAL_USART1_PRIORITY 7
#define ES32_SERIAL_USART1_PRIORITY 7
#define ES32_SERIAL_USART1_PRIORITY 7
#define ES32_SERIAL_USART1_PRIORITY 7

/*
* SPI driver system settings.
*/
#define ES32_SPI_USE_QSPI FALSE
#define ES32_SPI_USE_SPIM2 FALSE
#define ES32_SPI_USE_SPIS1 FALSE
#define ES32_SPI_USE_SPIS2 FALSE
#define ES32_SPI_QSPI_IRQ_PRIORITY 10
#define ES32_SPI_SPIM2_IRQ_PRIORITY 10
#define ES32_SPI_SPIS1_IRQ_PRIORITY 10
#define ES32_SPI_SPIS2_IRQ_PRIORITY 10
#define ES32_SPI_USE_SPI1 TRUE
#define ES32_SPI_USE_SPI2 TRUE

/*
* ST driver system settings.
Expand All @@ -151,6 +200,7 @@
#define ES32_USB_USE_USB1 TRUE
#define ES32_USB_USB1_IRQ_PRIORITY 13
#define ES32_USB_HOST_WAKEUP_DURATION 10
#define ES32_USE_USB_SOF_TRIM_HRC48 TRUE

/*
* ADC driver system settings.
Expand Down
3 changes: 2 additions & 1 deletion os/common/ext/CMSIS/ES32/FS026/md/md_adc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -161,7 +161,7 @@ void md_adc_sequence_conversion(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruc
ErrorStatus md_adc_software_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct)
{
//ADC input APB clock 12MHz
uint8_t clkdiv;
uint8_t clkdiv = 1;
uint16_t adc_data_1 = 0;
uint16_t adc_data_15 = 0;

Expand Down Expand Up @@ -277,6 +277,7 @@ ErrorStatus md_adc_optionbyte_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC
md_adc_enable_adcpower(ADCx);
md_adc_set_gain_factor(ADCx, adc_gain);
md_adc_set_offset_factor(ADCx, adc_offset);
(void)ADC_InitStruct;
return SUCCESS;
}

Expand Down
2 changes: 0 additions & 2 deletions os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c
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Original file line number Diff line number Diff line change
Expand Up @@ -337,8 +337,6 @@ void md_i2c_slave_receive(I2C_TypeDef *I2Cx, uint32_t Num, uint8_t *rxbuf)

while (!(md_i2c_is_active_flag_busy(I2Cx)));

printf("I2C1->STAT:%x\r\n", I2C1->STAT);

while (Num > 0)
{
while (!(md_i2c_is_active_flag_rxne(I2Cx)));
Expand Down
89 changes: 72 additions & 17 deletions os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -151,39 +151,28 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct)
{
uint32_t PLL0_Frequency;
uint32_t PLL0_Ref_Frequency;
uint32_t Current_Frequency;
double fration;

md_fc_set_read_latency(FC, MD_FC_WAIT_MORE_THAN_72Mhz);

if (RCU_InitStruct->HS_Clock & RCU_CON_PLL0ON)
md_rcu_enable_pll0(rcu);
else
md_rcu_disable_pll0(rcu);

if (RCU_InitStruct->HS_Clock & RCU_CON_HRC48ON)
md_rcu_enable_hrc48(rcu);
else
md_rcu_disable_hrc48(rcu);

if (RCU_InitStruct->HS_Clock & RCU_CON_HOSCON)
md_rcu_enable_hosc(rcu);
else
md_rcu_disable_hosc(rcu);

if (RCU_InitStruct->HS_Clock & RCU_CON_HRCON)
md_rcu_enable_hrc(rcu);
else
md_rcu_disable_hrc(rcu);

if (RCU_InitStruct->LS_Clock & RCU_LCON_LOSCON)
md_rcu_enable_losc(rcu);
else
md_rcu_disable_losc(rcu);

if (RCU_InitStruct->LS_Clock & RCU_LCON_LRCON)
md_rcu_enable_lrc(rcu);
else
md_rcu_disable_lrc(rcu);

//make sure HOSC CLK Ready
if ((RCU_InitStruct->HS_Clock & RCU_CON_HOSCON))
Expand All @@ -200,10 +189,7 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct)

md_rcu_set_mco_div(rcu, RCU_InitStruct->Mpre);
md_rcu_set_mco_source(rcu, RCU_InitStruct->Msw);
md_rcu_set_pclk_div(rcu, RCU_InitStruct->Ppre);
md_rcu_set_hclk_div(rcu, RCU_InitStruct->Hpre);
md_rcu_set_system_clock_source(rcu, RCU_InitStruct->Sw);


switch ((RCU_InitStruct->PllSrc))
{
case MD_RCU_PLLSRC_HRC :
Expand All @@ -227,9 +213,58 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct)
fration = (double)md_rcu_get_pll0_fn(rcu) + ((double)md_rcu_get_pll0_fk(rcu) / (1 << 19));
PLL0_Frequency = (uint32_t)(PLL0_Ref_Frequency * fration / (1 << (md_rcu_get_pll0_fm(rcu) + 3)));

/* System Frequency */
/*
Determine whether it is a PLL that needs to be switched.
If it is a PLL, it is a frequency increase buffering process.
Otherwise, if it is not a PLL, it is a frequency decrease buffering process.
*/
if(RCU_InitStruct->Sw==MD_RCU_SW_SYSCLK_PLL0)
{
/*
PLL frequency rise buffer processing, the trigger environment is when it is necessary to
switch to the PLL frequency greater than or equal to 48M, if the current or set HCLK prescaler is 1,
the HCLK prescaler will be set to 2 first and then the system frequency will be switched.
After the switch is completed Will wait for 10us before resetting the HCLK prescaler.
*/
if((PLL0_Frequency>=48000000) &&
((md_rcu_get_hclk_div(RCU)==MD_RCU_HPRE_SYSCLK_DIV_1)||
(RCU_InitStruct->Hpre==MD_RCU_HPRE_SYSCLK_DIV_1)))
{
SystemFrequency_AHBClk = PLL0_Frequency>>1;
md_tick_init(MD_SYSTICK_CLKSRC_HCLK);
md_rcu_set_hclk_div(rcu,MD_RCU_HPRE_SYSCLK_DIV_2);
md_rcu_set_system_clock_source(rcu, RCU_InitStruct->Sw);
md_tick_wait10us(1,1);
}
}
else
{
/*
PLL frequency reduction buffer processing, the triggering environment is when it is not
necessary to switch the PLL frequency and the current system frequency is higher than 48M,
the HCLK prescaler will first be set to 2 to reduce the HCLK speed, and then the system frequency
will be switched to a low frequency after the reduction is completed. Finally reset the
HCLK prescaler.
*/
Current_Frequency = md_rcu_get_current_system_frequency(RCU)*1000000;
if(Current_Frequency>=48000000)
{
SystemFrequency_AHBClk = Current_Frequency>>1;
md_tick_init(MD_SYSTICK_CLKSRC_HCLK);
md_rcu_set_hclk_div(rcu,MD_RCU_HPRE_SYSCLK_DIV_2);
md_tick_wait10us(1,1);
}
}

md_rcu_set_system_clock_source(rcu, RCU_InitStruct->Sw);

md_rcu_set_hclk_div(rcu, RCU_InitStruct->Hpre);

md_rcu_set_pclk_div(rcu, RCU_InitStruct->Ppre);

switch (md_rcu_get_current_system_clock(rcu)) /* System clock switch(SYSCLK) */
{

case MD_RCU_SWS_SYSCLK_HRC: /*================= HRC selected as system clock*/
SystemCoreClock = (uint32_t)(__HRC);
break;
Expand Down Expand Up @@ -283,6 +318,26 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct)
md_fc_set_read_latency(FC, MD_FC_WAIT_BETWEEN_24MHz_AND_48Mhz);
else
md_fc_set_read_latency(FC, MD_FC_WAIT_LESS_THAN_24MHz);

if (!(RCU_InitStruct->HS_Clock & RCU_CON_PLL0ON))
md_rcu_disable_pll0(rcu);

if (!(RCU_InitStruct->HS_Clock & RCU_CON_HRC48ON))
md_rcu_disable_hrc48(rcu);

if (!(RCU_InitStruct->HS_Clock & RCU_CON_HOSCON))
md_rcu_disable_hosc(rcu);

if (!(RCU_InitStruct->HS_Clock & RCU_CON_HRCON))
md_rcu_disable_hrc(rcu);

if (!(RCU_InitStruct->LS_Clock & RCU_LCON_LOSCON))
md_rcu_disable_losc(rcu);

if (!(RCU_InitStruct->LS_Clock & RCU_LCON_LRCON))
md_rcu_disable_lrc(rcu);

md_tick_init(MD_SYSTICK_CLKSRC_HCLK);
}

/**
Expand Down
5 changes: 5 additions & 0 deletions os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,11 @@ STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_uart.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_spi.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_dma.c \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c

STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
Expand Down

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