* Remove labels on ESD diodes so they are now recognized as regular
  d(p)antenna diodes
* Increase width to minimum 0.48µm to account for new rule not yet in
  DRC check.

Signed-off-by: Staf Verhaegen <staf.verhaegen@chipflow.io>

OpenROAD, OpenROAD flow scripts, Qucs-S added as supported EDA tools.

Signed-off-by: Krzysztof Herman <141824113+KrzysztofHerman@users.noreply.github.com>

…nto dev

Merging synced dev  branch from own forc to local repo

-added partial implementation of class Pin from PyCell API
-added partial implementation of class Term from PyCell API
-added support for pins/terminals
-added support for XOR geometric transformation
-added support for text alignment/orientation
-fixed dbLayerXorList from geometry.py
-added support of npn13G2L and npn13G2V
-extended documentation

Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>

Klayout PyCell integration

Some updates on top of IHP-GmbH#121

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>

Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>

Layout rule manual update

Signed-off-by: FaragElsayed2 <farag_agoor@mabrains.com>

…vs_dev2

…vs_dev2

Removing NO DRC filter for LVS runset for all layers

Remove NO_DRC filtering

…V mosfets

Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>

…nto dev

…m), symbols modified, some testcases modified

Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>

-added PyCell parameter type bool
-added partial implementation for PyCell API class Net
-added partial implementation for PyCell API class Path
-added partial implementation for PyCell API class ShapeFilter
-added support for Net's
-added generic registering of IHP PyCell's in Klayout
-added support for inductor2, inductor2_sc, inductor2_sp, inductor3,
 inductor3_sc and inductor3_sp
-updated documentation

Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>

-fixed merge-error

Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>

Klayout PyCell integration

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

…sistent w/ internal implementation

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

-fix wrong assignment: re-assign pins, terms and nets from PyCell-instances to cell-instances for
 multi-cell instances of the same PyCell

Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>

HV-MOS transistors PCells

Klayout PyCell integration

…eparate files)

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

This script can be called in Klayout's batch mode and generates a
GDS file with a sealring included. The width and height of the ring
are configurable via arguments.

Example call:

    klayout -n sg13g2 -zz -r sealring.py \
            -rd width=1300.0 -rd height=1300.0 \
            -rd output=macros/sealring.gds.gz

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>

Symbols update

dantenna and dpantenna PCells integration

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

-fixed pin label creation by removing extra text generation
-added missing self-argument in class Box

Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>

Klayout PyCell integration

Signed-off-by: Daniel Arevalos <daniel.arevalos@sansano.usm.cl>

The DRC report had multiple violations included which are
relate to unclean calculation of the chip border.

Based-on: Andreas Krinke <andreas.krinke@tu-dresden.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

This script calculates and reports the density for multiple important
layers and can help to see which layers will violatie fill rules.

Based-on: Krzystof Herman <herman@ihp-microelectronics.com>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

Via stack PCell integration

libs.tech: klayout: Add Python script to generate Sealring files

Update Filler Checks

Global min./max. Metal(n) density values are 35% and 60%. The
previous 25% and 75% are only valid for 800x800 chip areas.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

libs.tech: klayout: Fix Metal density min/max values

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

…(stdcell, sram)

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

Removing reference to merged.lef which does not exist.

Signed-off-by: Peter <46405338+gadfort@users.noreply.github.com>

…q) = 5nm

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

…om .lyp file

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

updated PDK contents

-added support for fgAnd, fgNot andfgSize
-fixed dbLayerSize
-updated documentation

Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>

Signed-off-by: Sergei Andreev <116548619+sergeiandreyev@users.noreply.github.com>

- maximal DRC script supports ~75% of rules
- rename DRC script parameters for OpenROAD compatibility
    - logfile -> log_file
    - gdsfile -> in_gds
    - outfile -> report_file
- DRC script parameter "cell" is now optional
- output number of DRC errors at the end
- DRC script no longer depends on layout dbu
    - all lengths are given in micrometers
- add limits to rule descriptions, e.g., "Min. GatPoly width = 0.13"

Signed-off-by: Andreas Krinke <andreas.krinke@gmx.de>

Update KLayout DRC scripts

Klayout PyCell integration

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

…tation

libs.tech: klayout: macros: Fix intentation

added LVS in PDK contents section

Signed-off-by: Sergei Andreev <116548619+sergeiandreyev@users.noreply.github.com>

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

Remove merged.lef from klayout setup

OpenROAD requires the sg13g2.map file to correctly place each layer.
Fix this here to not overwrite manually changes in
OpenROAD-Flow-Scripts.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

This file was copied from the OpenROAD-flow-scripts repository
and should be maintained and kept here.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

OpenROAD-flow-scripts will search and replace for
<lef-files>.*</lef-files>. Therefore, keep it empty in this syntax.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

libs.tech: Klayout: tech: Add layer map

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

added 'Digital' tool in PDK contents

Signed-off-by: Sergei Andreev <116548619+sergeiandreyev@users.noreply.github.com>

Added 'Digital' IHP130 cells as submodule

Signed-off-by: Sergei Andreev <andreev@ihp-microelectronics.com>

Signed-off-by: FaragElsayed2 <farag_agoor@mabrains.com>

Dev

…ucs-s examples updated

Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>