NGSPICE model referencing based on .spiceinit

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "ihp-sg13g2/libs.tech/digital"]
+	path = ihp-sg13g2/libs.tech/digital
+	url = git@github.com:hneemann/IHP130.git

README.md

@@ -39,10 +39,12 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
     * SPICE Netlist
     * Verilog
 * IO cellset
+    * CDL
     * GDSII
     * LEF
-    * Liberty (dummy)
+    * Liberty
     * SPICE Netlist
+    * Verilog
 * SRAM cellset
     * CDL
     * GDSII
@@ -53,13 +55,13 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
     * GDSII
 * KLayout tool data:
     * layer property and tech files
-    * DRC rules (minimal set)
-    * PyCells
-       * initial version of the wrapper API
-       * sample cells
-* Pcells (for reference only) `libs.tech/pycell`
+    * DRC rules (minimal/maximal set)
+    * LVS rules
+    * PyCells (1st priority) 
 * MOS/HBT/Passive device models for ngspice/Xyce
 * xschem: primitive device symbols, settings and testbenches
+* Qucs-S: primitive device symbols, settings and testbenches
+* Digital: stdcells
 * OpenEMS: tutorials, scripts, documentation
 * SG13G2 Process specification & Layout Rules
 * MOS/HBT Measurements in MDM format
@@ -83,6 +85,10 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
     * Source: https://github.com/KLayout/klayout
 * OpenEMS
     * Source: https://github.com/thliebig/openEMS-Project
+* OpenROAD
+    * Source: https://github.com/The-OpenROAD-Project/OpenROAD
+* OpenROAD-flow-scripts
+    * Source: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
 
 ## Contributing
 

ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_iocell.cdl → ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl

@@ -28,7 +28,7 @@
 .PARAM
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    DCNDiode
 * View Name:    schematic
 ************************************************************************
@@ -39,7 +39,7 @@ DD0 anode cathode dantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    DCPDiode
 * View Name:    schematic
 ************************************************************************
@@ -50,7 +50,7 @@ DD0 anode cathode dpantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    inv_x1
 * View Name:    schematic
 ************************************************************************
@@ -62,7 +62,7 @@ MP0 nq i vdd vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    LevelUp
 * View Name:    schematic
 ************************************************************************
@@ -80,7 +80,7 @@ MP1 net4 net3 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    nor2_x1
 * View Name:    schematic
 ************************************************************************
@@ -94,7 +94,7 @@ MP0 nq i1 net1 vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    nand2_x1
 * View Name:    schematic
 ************************************************************************
@@ -108,7 +108,7 @@ MN0 nq i1 net1 vss sg13_lv_nmos m=1 w=3.93u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    GateDecode
 * View Name:    schematic
 ************************************************************************
@@ -123,7 +123,7 @@ XI1 core en net2 vdd vss / nand2_x1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    SecondaryProtection
 * View Name:    schematic
 ************************************************************************
@@ -136,7 +136,7 @@ DD1 core plus dpantenna m=1 w=780.00n l=4.98u a=3.884p p=11.52u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    LevelDown
 * View Name:    schematic
 ************************************************************************
@@ -151,7 +151,7 @@ MP1 core net2 vdd vdd sg13_lv_pmos m=1 w=4.75u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadInOut30mA
 * View Name:    schematic
 ************************************************************************
@@ -167,7 +167,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    LevelUpInv
 * View Name:    schematic
 ************************************************************************
@@ -185,7 +185,7 @@ MP1 net4 net3 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    GateLevelUpInv
 * View Name:    schematic
 ************************************************************************
@@ -197,7 +197,7 @@ XI0 core iovdd ngate vdd vss / LevelUpInv
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadOut4mA
 * View Name:    schematic
 ************************************************************************
@@ -212,7 +212,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler10000
 * View Name:    schematic
 ************************************************************************
@@ -222,7 +222,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadVss
 * View Name:    schematic
 ************************************************************************
@@ -234,7 +234,7 @@ XI1 iovss vss iovss / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadIOVss
 * View Name:    schematic
 ************************************************************************
@@ -246,7 +246,7 @@ DD1 iovss iovdd dpantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadOut16mA
 * View Name:    schematic
 ************************************************************************
@@ -261,7 +261,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    RCClampResistor
 * View Name:    schematic
 ************************************************************************
@@ -331,7 +331,7 @@ RR0 pin1 net1 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    Clamp_N43N43D4R
 * View Name:    schematic
 ************************************************************************
@@ -513,7 +513,7 @@ MN0<172> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    RCClampInverter
 * View Name:    schematic
 ************************************************************************
@@ -526,7 +526,7 @@ MP0 out in supply supply sg13_hv_pmos m=1 w=350.000u l=500.0n ng=50
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadIOVdd
 * View Name:    schematic
 ************************************************************************
@@ -539,7 +539,7 @@ XI1 net1 iovss net2 iovdd / RCClampInverter
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadTriOut30mA
 * View Name:    schematic
 ************************************************************************
@@ -554,7 +554,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadTriOut16mA
 * View Name:    schematic
 ************************************************************************
@@ -569,7 +569,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadInOut16mA
 * View Name:    schematic
 ************************************************************************
@@ -585,7 +585,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler200
 * View Name:    schematic
 ************************************************************************
@@ -595,7 +595,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler2000
 * View Name:    schematic
 ************************************************************************
@@ -605,7 +605,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadOut30mA
 * View Name:    schematic
 ************************************************************************
@@ -620,7 +620,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadInOut4mA
 * View Name:    schematic
 ************************************************************************
@@ -636,7 +636,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    Clamp_N20N0D
 * View Name:    schematic
 ************************************************************************
@@ -649,7 +649,7 @@ RR1 iovss net2 rppd 1.959K m=1 l=3.54u w=500n ps=180n
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    Clamp_P20N0D
 * View Name:    schematic
 ************************************************************************
@@ -662,7 +662,7 @@ RR0 net2 iovdd rppd 6.768K m=1 l=12.9u w=500n ps=180n
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadAnalog
 * View Name:    schematic
 ************************************************************************
@@ -677,7 +677,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler4000
 * View Name:    schematic
 ************************************************************************
@@ -687,7 +687,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Corner
 * View Name:    schematic
 ************************************************************************
@@ -697,7 +697,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler400
 * View Name:    schematic
 ************************************************************************
@@ -707,7 +707,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadTriOut4mA
 * View Name:    schematic
 ************************************************************************
@@ -722,7 +722,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadIn
 * View Name:    schematic
 ************************************************************************
@@ -735,7 +735,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadVdd
 * View Name:    schematic
 ************************************************************************
@@ -747,7 +747,7 @@ DD0 iovss vdd dantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler1000
 * View Name:    schematic
 ************************************************************************

ihp-sg13g2/libs.ref/sg13g2_io/doc/README.md

@@ -14,7 +14,7 @@ This is the sg13g2_io library. The following files are included in this library:
 These files are generated from python scripts of the Chips4Makers based IHP SG13G2
 PDK. The code can be found in the
 [c4m-pdk-ihpsg13g2](https://gitlab.com/Chips4Makers/c4m-pdk-ihpsg13g2.git) repo.
-This library is built from version `0.0.3` of that source code.
+This library is built from version `0.0.4` of that source code.
 The `README.md` file of this project explains how to use the code in there. The whole
 build of the files plus preparation of the files described above for upstreaming can be
 generated with the command `pdm doit patch4upstream`.