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Adding support for Microchip PIC32CX SG devices
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@MyGh64605
MyGh64605 committed Jun 24, 2024
1 parent 22f2a0d commit e25427c
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Showing 101 changed files with 329 additions and 18,450 deletions.
257 changes: 0 additions & 257 deletions mplabx/pic32cxsg/include/pic32cxsg41/component/ac.h
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336 changes: 0 additions & 336 deletions mplabx/pic32cxsg/include/pic32cxsg41/component/adc.h
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151 changes: 0 additions & 151 deletions mplabx/pic32cxsg/include/pic32cxsg41/component/aes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -26,27 +26,6 @@
/* ************************************************************************** */

/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
uint32_t :1; /*!< bit: 15 Reserved */
uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AES_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_CTRLA_RESETVALUE _UINT32_(0x00) /* (AES_CTRLA) Control A Reset Value */

#define AES_CTRLA_SWRST_Pos _UINT32_(0) /* (AES_CTRLA) Software Reset Position */
Expand Down Expand Up @@ -136,19 +115,6 @@ typedef union {


/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
uint8_t NEWMSG:1; /*!< bit: 1 New message */
uint8_t EOM:1; /*!< bit: 2 End of message */
uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_CTRLB_RESETVALUE _UINT8_(0x00) /* (AES_CTRLB) Control B Reset Value */

#define AES_CTRLB_START_Pos _UINT8_(0) /* (AES_CTRLB) Start Encryption/Decryption Position */
Expand All @@ -167,17 +133,6 @@ typedef union {


/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AES_INTENCLR) Interrupt Enable Clear Reset Value */

#define AES_INTENCLR_ENCCMP_Pos _UINT8_(0) /* (AES_INTENCLR) Encryption Complete Interrupt Enable Position */
Expand All @@ -190,17 +145,6 @@ typedef union {


/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_INTENSET_RESETVALUE _UINT8_(0x00) /* (AES_INTENSET) Interrupt Enable Set Reset Value */

#define AES_INTENSET_ENCCMP_Pos _UINT8_(0) /* (AES_INTENSET) Encryption Complete Interrupt Enable Position */
Expand All @@ -213,17 +157,6 @@ typedef union {


/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
__I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AES_INTFLAG) Interrupt Flag Status Reset Value */

#define AES_INTFLAG_ENCCMP_Pos _UINT8_(0) /* (AES_INTFLAG) Encryption Complete Position */
Expand All @@ -236,16 +169,6 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register


/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_DATABUFPTR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_DATABUFPTR_RESETVALUE _UINT8_(0x00) /* (AES_DATABUFPTR) Data buffer pointer Reset Value */

#define AES_DATABUFPTR_INDATAPTR_Pos _UINT8_(0) /* (AES_DATABUFPTR) Input Data Pointer Position */
Expand All @@ -255,16 +178,6 @@ typedef union {


/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AES_DBGCTRL) Debug control Reset Value */

#define AES_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AES_DBGCTRL) Debug Run Position */
Expand All @@ -274,11 +187,6 @@ typedef union {


/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_KEYWORD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_KEYWORD_RESETVALUE _UINT32_(0x00) /* (AES_KEYWORD) Keyword n Reset Value */

#define AES_KEYWORD_KEYWORD_Pos _UINT32_(0) /* (AES_KEYWORD) Key Word Value Position */
Expand All @@ -288,12 +196,6 @@ typedef union {


/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_INDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_INDATA_RESETVALUE _UINT32_(0x00) /* (AES_INDATA) Indata Reset Value */

#define AES_INDATA_INDATA_Pos _UINT32_(0) /* (AES_INDATA) Data Value Position */
Expand All @@ -303,12 +205,6 @@ typedef union {


/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_INTVECTV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_INTVECTV_RESETVALUE _UINT32_(0x00) /* (AES_INTVECTV) Initialisation Vector n Reset Value */

#define AES_INTVECTV_INTVECTV_Pos _UINT32_(0) /* (AES_INTVECTV) Initialization Vector Value Position */
Expand All @@ -318,12 +214,6 @@ typedef union {


/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_HASHKEY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_HASHKEY_RESETVALUE _UINT32_(0x00) /* (AES_HASHKEY) Hash key n Reset Value */

#define AES_HASHKEY_HASHKEY_Pos _UINT32_(0) /* (AES_HASHKEY) Hash Key Value Position */
Expand All @@ -333,12 +223,6 @@ typedef union {


/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_GHASH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_GHASH_RESETVALUE _UINT32_(0x00) /* (AES_GHASH) Galois Hash n Reset Value */

#define AES_GHASH_GHASH_Pos _UINT32_(0) /* (AES_GHASH) Galois Hash Value Position */
Expand All @@ -348,12 +232,6 @@ typedef union {


/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_CIPLEN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_CIPLEN_RESETVALUE _UINT32_(0x00) /* (AES_CIPLEN) Cipher Length Reset Value */

#define AES_CIPLEN_CIPLEN_Pos _UINT32_(0) /* (AES_CIPLEN) Cipher Length Position */
Expand All @@ -363,42 +241,13 @@ typedef union {


/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_RANDSEED_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define AES_RANDSEED_RESETVALUE _UINT32_(0x00) /* (AES_RANDSEED) Random Seed Reset Value */

#define AES_RANDSEED_RANDSEED_Pos _UINT32_(0) /* (AES_RANDSEED) Random Seed Position */
#define AES_RANDSEED_RANDSEED_Msk (_UINT32_(0xFFFFFFFF) << AES_RANDSEED_RANDSEED_Pos) /* (AES_RANDSEED) Random Seed Mask */
#define AES_RANDSEED_RANDSEED(value) (AES_RANDSEED_RANDSEED_Msk & (_UINT32_(value) << AES_RANDSEED_RANDSEED_Pos)) /* Assigment of value for RANDSEED in the AES_RANDSEED register */
#define AES_RANDSEED_Msk _UINT32_(0xFFFFFFFF) /* (AES_RANDSEED) Register Mask */

/** \brief AES hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
__IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
RoReg8 Reserved1[0x2];
__O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
RoReg8 Reserved2[0xC];
__IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
RoReg8 Reserved3[0x10];
__IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
__IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
RoReg8 Reserved4[0x4];
__IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
__IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
} Aes;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/** \brief AES register offsets definitions */
#define AES_CTRLA_REG_OFST _UINT32_(0x00) /* (AES_CTRLA) Control A Offset */
Expand Down
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