refactor (platform): introduces kintex7 specific platform file, integ…

…rates into board_kasli (#25)

With this change we now expect the helper Si549 to generate the 62.49MHz clock directly.

board/kasli/wr_kasli_pkg.vhd

@@ -176,7 +176,7 @@ package wr_kasli_pkg is
       -- Clocks/resets
       ---------------------------------------------------------------------------
       -- Clock inputs from the board
-      clk_20m_vcxo_i         : in    std_logic;
+      clk_62m5_vcxo_i        : in    std_logic;
       clk_125m_gtp_p_i       : in    std_logic;
       clk_125m_gtp_n_i       : in    std_logic;
       clk_125m_bootstrap_p_i : in    std_logic;
@@ -430,7 +430,7 @@ package wr_kasli_pkg is
       -- Clocks/resets
       ---------------------------------------------------------------------------
       -- Clock inputs from the board
-      clk_20m_vcxo_i         : in    std_logic;
+      clk_62m5_vcxo_i        : in    std_logic;
       clk_125m_gtp_p_i       : in    std_logic;
       clk_125m_gtp_n_i       : in    std_logic;
       clk_125m_bootstrap_p_i : in    std_logic;

board/kasli/wrc_board_kasli.vhd

@@ -83,7 +83,7 @@ entity wrc_board_kasli is
     -- Clocks/resets
     ---------------------------------------------------------------------------
     -- Clock inputs from the board
-    clk_20m_vcxo_i         : in    std_logic;
+    clk_62m5_vcxo_i        : in    std_logic;
     clk_125m_gtp_n_i       : in    std_logic;
     clk_125m_gtp_p_i       : in    std_logic;
     clk_125m_bootstrap_p_i : in    std_logic;
@@ -458,7 +458,7 @@ begin  -- architecture struct
       g_wb_crossbar_mask_cfg    => c_wb_crossbar_mask_kasli_periph
     )
     port map (
-      clk_20m_vcxo_i         => clk_20m_vcxo_i,
+      clk_62m5_vcxo_i        => clk_62m5_vcxo_i,
       clk_125m_gtp_p_i       => clk_125m_gtp_p_i,
       clk_125m_gtp_n_i       => clk_125m_gtp_n_i,
       clk_125m_bootstrap_p_i => clk_125m_bootstrap_p_i,

board/kasli/xwrc_board_kasli.vhd

@@ -93,7 +93,7 @@ entity xwrc_board_kasli is
     -- Clocks/resets
     ---------------------------------------------------------------------------
     -- Clock inputs from the board
-    clk_20m_vcxo_i         : in    std_logic;
+    clk_62m5_vcxo_i        : in    std_logic;
     clk_125m_gtp_p_i       : in    std_logic;
     clk_125m_gtp_n_i       : in    std_logic;
     clk_125m_bootstrap_p_i : in    std_logic;
@@ -282,7 +282,6 @@ architecture struct of xwrc_board_kasli is
   signal clk_pll_aux    : std_logic_vector(3 downto 0);
   signal pll_locked     : std_logic;
   signal pll_sys_locked : std_logic;
-  signal clk_10m_ext    : std_logic;
 
   -- Reset logic
   signal sys_rstlogic_clk_in  : std_logic_vector(3 downto 0);
@@ -332,12 +331,6 @@ architecture struct of xwrc_board_kasli is
   signal phy16_to_wrc   : t_phy_16bits_to_wrc;
   signal phy16_from_wrc : t_phy_16bits_from_wrc;
 
-  -- External reference
-  signal ext_ref_mul         : std_logic;
-  signal ext_ref_mul_locked  : std_logic;
-  signal ext_ref_mul_stopped : std_logic;
-  signal ext_ref_rst         : std_logic;
-
   -- GP1 master port wishbone slave connection
   signal wb_m01_slave_in  : t_wishbone_slave_in;
   signal wb_m01_slave_out : t_wishbone_slave_out;
@@ -551,43 +544,47 @@ begin  -- architecture struct
   -- Platform-dependent part (PHY, PLLs, buffers, etc)
   -----------------------------------------------------------------------------
 
-  u_xwrc_platform : component xwrc_platform_xilinx
+  u_xwrc_platform_kintex7 : component xwrc_platform_kintex7
     generic map (
-      g_fpga_family                => "kintex7",
+      g_with_main_pll              => TRUE,
+      g_with_helper_pll            => FALSE,
+      g_dmtd_div2                  => FALSE,
       g_with_external_clock_input  => FALSE,
       g_with_bootstrap_clock_input => TRUE,
-      g_use_default_plls           => TRUE,
       g_aux_pll_cfg                => g_aux_pll_cfg,
       g_simulation                 => g_simulation
     )
     port map (
-      -- clock / reset
+      -- PLL reset
       areset_n_i             => pll_areset_n,
-      clk_20m_vcxo_i         => clk_20m_vcxo_i,
+      -- Transceiver / main PLL ref clk
       clk_125m_gtp_p_i       => clk_125m_gtp_p_i,
       clk_125m_gtp_n_i       => clk_125m_gtp_n_i,
+      -- Main PLL bootstrap clk + select
       clk_125m_bootstrap_i   => clk_125m_bootstrap,
       clk_sys_sel_i          => pll_clk_sys_sel,
+      -- Helper clock (direct passthrough)
+      clk_62m5_dmtd_i        => clk_62m5_vcxo_i,
+      clk_dmtd_locked_i      => '1',
+      -- SFP
       sfp_txn_o              => sfp_txn_o,
       sfp_txp_o              => sfp_txp_o,
       sfp_rxn_i              => sfp_rxn_i,
       sfp_rxp_i              => sfp_rxp_i,
       sfp_tx_fault_i         => sfp_tx_fault,
       sfp_los_i              => sfp_los,
       sfp_tx_disable_o       => sfp_tx_disable,
+      -- output clocks
       clk_62m5_sys_o         => clk_pll_62m5,
       clk_125m_ref_o         => clk_pll_125m,
       clk_62m5_dmtd_o        => clk_pll_dmtd,
       clk_pll_aux_o          => clk_pll_aux,
+      -- lock status
       pll_locked_o           => pll_locked,
       pll_aux_locked_o       => pll_sys_locked,
-      clk_10m_ext_o          => clk_10m_ext,
+      -- PHY interface
       phy16_o                => phy16_to_wrc,
-      phy16_i                => phy16_from_wrc,
-      ext_ref_mul_o          => ext_ref_mul,
-      ext_ref_mul_locked_o   => ext_ref_mul_locked,
-      ext_ref_mul_stopped_o  => ext_ref_mul_stopped,
-      ext_ref_rst_i          => ext_ref_rst
+      phy16_i                => phy16_from_wrc
     );
 
   clk_sys_62m5_o <= clk_pll_62m5;
@@ -725,10 +722,6 @@ begin  -- architecture struct
       clk_sys_i            => clk_pll_62m5,
       clk_dmtd_i           => clk_pll_dmtd,
       clk_ref_i            => clk_pll_125m,
-      clk_ext_mul_i        => ext_ref_mul,
-      clk_ext_mul_locked_i => ext_ref_mul_locked,
-      clk_ext_stopped_i    => ext_ref_mul_stopped,
-      clk_ext_rst_o        => ext_ref_rst,
       rst_n_i              => rst_sys_62m5_n,
       -- Helper PLL updates
       dac_hpll_load_p1_o => dac_pll_load_p1(1),

platform/xilinx/wr_xilinx_pkg.vhd

@@ -367,4 +367,55 @@ package wr_xilinx_pkg is
     );
   end component;
 
+  component xwrc_platform_kintex7 is
+    generic (
+      g_with_main_pll              : boolean := TRUE;
+      g_with_helper_pll            : boolean := TRUE;
+      g_dmtd_div2                  : boolean := TRUE;
+      g_with_external_clock_input  : boolean := FALSE;
+      g_with_bootstrap_clock_input : boolean := FALSE;
+      g_aux_pll_cfg                : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT;
+      g_simulation                 : integer := 0);
+    port (
+      areset_n_i             : in  std_logic;
+      clk_10m_ext_i          : in  std_logic             := '0';
+      clk_125m_gtp_p_i       : in  std_logic;
+      clk_125m_gtp_n_i       : in  std_logic;
+      clk_125m_bootstrap_i   : in  std_logic             := '0';
+      clk_sys_sel_i          : in  std_logic             := '1';
+      clk_62m5_sys_i         : in  std_logic             := '0';
+      clk_sys_locked_i       : in  std_logic             := '1';
+      clk_20m_vcxo_i         : in  std_logic             := '0';
+      clk_125m_dmtd_i        : in  std_logic             := '0';
+      clk_62m5_dmtd_i        : in  std_logic             := '0';
+      clk_dmtd_locked_i      : in  std_logic             := '1';
+      clk_125m_ext_i         : in  std_logic             := '0';
+      clk_ext_locked_i       : in  std_logic             := '1';
+      clk_ext_stopped_i      : in  std_logic             := '0';
+      clk_ext_rst_o          : out std_logic;
+      sfp_txn_o              : out std_logic;
+      sfp_txp_o              : out std_logic;
+      sfp_rxn_i              : in  std_logic;
+      sfp_rxp_i              : in  std_logic;
+      sfp_tx_fault_i         : in  std_logic             := '0';
+      sfp_los_i              : in  std_logic             := '0';
+      sfp_tx_disable_o       : out std_logic;
+      clk_pll_aux_o          : out std_logic_vector(3 downto 0);
+      pll_aux_locked_o       : out std_logic;
+      clk_62m5_sys_o         : out std_logic;
+      clk_125m_ref_o         : out std_logic;
+      clk_20m_o              : out std_logic;
+      clk_ref_locked_o       : out std_logic;
+      clk_62m5_dmtd_o        : out std_logic;
+      clk_250m_dmtd_over_o   : out std_logic;
+      pll_locked_o           : out std_logic;
+      clk_10m_ext_o          : out std_logic;
+      phy16_o                : out t_phy_16bits_to_wrc;
+      phy16_i                : in  t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
+      ext_ref_mul_o          : out std_logic;
+      ext_ref_mul_locked_o   : out std_logic;
+      ext_ref_mul_stopped_o  : out std_logic;
+      ext_ref_rst_i          : in  std_logic             := '0');
+end component;
+
 end wr_xilinx_pkg;